Abstract: A system for efficiently developing an LSI. A developing system includes a developing apparatus and a support center, which are connected to each other via the Internet. The host computer of the developing apparatus designs the software of a system LSI in accordance with a user's instruction. An emulator debugger sends design data to the support center. The support center performs a predetermined process on the received design data and notifies the processing result to a host computer via the Internet.

Abstract: A method and computer program for testing a design of a circuit comprises providing a model of the design; providing a first property for the design, wherein the first property describes a first behavior; checking the model using the first property and an environment of the design at a reset state until an example of the first behavior occurs; providing a second property for the design, wherein the second property describes a second behavior; and checking the model using the second property and an environment of the design at a state when the example of the first behavior occurs.

Abstract: A board design aiding apparatus that simplifies a designed printed wiring board to predict a displacement quantity of the printed wiring board includes a layer thickness calculation section 21 for obtaining a mean thickness of an area of a board by a prescribed rule for an essential material forming a layer at each layer for constructing the printed wiring board, and a laminate model forming section 22 for forming a simple laminate model by laminating layers having layer thickness calculated by the layer thickness calculation section 21.

Abstract: A method, module, and program product for detecting signal strengths in a hardware description language, such as Verilog, that does not provide for such detection. The method includes the steps of creating a wired net configuration that provides for a data input signal and a controlled reference signal; varying the controlled reference signal based on a desired signal strength to be detected; and comparing the input signal with the controlled reference signal to determine if the desired signal strength has been detected.

Abstract: In order to realize a means for acquiring three-dimensional shape information about patterns by nondestruction and evaluate a relationship between the three-dimensional shape information about these patterns and device properties, a semiconductor device pattern evaluating system is provided with a feature index calculating means for quantifying a property of a three-dimensional shape of a pattern to be evaluated, as feature index, a database that records therein a relationship between the feature index of each three-dimensional pattern shape and a device property of a circuit containing patterns each having the feature index, and a device property estimating means for estimating a property of a device circuit formed by the pattern to be evaluated, on the basis of the feature index of the three-dimensional pattern shape, which have been quantified by the feature index calculating means, and the information recorded in the database.

Abstract: A method is disclosed for completing a flip chip package design by re-using mask designs in a tool library. The method comprises analyzing one or more input/out bump locations of a chip, analyzing one or more solder ball locations of a package hosting the chip with regard to a predetermined printed circuit board, and designing the package hosting the chip by using a tool library containing one or more existing mask designs for re-use, wherein when one or more existing mask designs are used for the package, at least one custom connection layer of the package is redesigned when needed for connecting the chip to the printed circuit board without producing a full set of new masks for the package.

Abstract: A method of correcting a finish pattern dimension by using OPC when a design pattern is formed on a wafer, including selecting and determining a first design pattern included in the design pattern; acquiring a measurement value of a first finish pattern dimension when the first design pattern is formed on a wafer; determining a first calculation model by using the first finish pattern dimension; selecting and determining a second design pattern from the design pattern except for the first design pattern; performing first simulation by using the first calculation model, and calculating a second finish pattern dimension when the second design pattern is formed on a wafer; determining a second calculation model for performing second simulation which is faster than the first simulation, by using the first and second finish pattern dimensions; and performing the second simulation by using the second calculation model, and calculating a third finish pattern dimension of a third design pattern of the design pattern

Abstract: The present invention relates to a graphical user interface for a system that compiles MATLAB models for synthesis into register transfer level code. The graphical user interface provides a visual representation of the design in a manner that allows the user to more easily understand the algorithm being modeled. From this interface, the user may also modify the type, size and dimensions of variables from dialog boxes. The system allows the user to efficiently compare and verify a fixed-point design versus the MATLAB design. The interface allows the user to then make further changes to the design, or synthesize the design into a register transfer level file.

Abstract: A development environment includes a graphical design tool and a build agent. The graphical design tool allows a designer to design a primary logic component of a circuit. The graphical design tool generates modules using a hardware description language to represent the primary logic component of the circuit. The modules include abstract references to infrastructure for the circuit. The build agent synthesizes the modules into netlists and merges the netlists with a description of the infrastructure for the circuit. The infrastructure is generated in a development environment separate from the graphical design tool. The build agent includes an adjuster that adjusts the modules. The adjustment to the modules includes replacing the abstract references to the infrastructure with actual references utilized within the infrastructure.

Abstract: Some embodiments of the invention provide a router that can define a route that has different widths along different directions on the same layer. To facilitate the creation of such a route, some embodiments adaptively define the shape of interconnect-line ends (i.e., the shape of route-segment ends) on a particular layer based on the routing directions available on the particular layer. By so defining these shapes, these embodiments improve the alignment of route segments that have differing widths. In other words, dynamically defining the interconnect-line ends improves the shape of a route at bends along which the route transition from one width to another. Also, to facilitate the creation of a route with different widths and/or spacing in different directions on a particular layer, some embodiments define, for each available routing direction on the particular layer, an “unroutable” bloated region about a previously defined geometry (e.g.

Abstract: A mechanism has been developed by which the impact on speed from back end-of-line interconnect layers may be characterized. A method for designing interconnect layers of an integrated circuit includes coupling a capacitive load to a speed sensing circuit to measure a delay corresponding to an interconnect structure of an integrated circuit design, selectively configuring the capacitive load by selectively coupling at least one of a plurality of capacitive structures, the capacitive structures including at least a portion of a plurality of metal layers. The capacitive load is representative of the interconnect structure. The method includes measuring the delay corresponding to the capacitive load to characterize at least one layer of the interconnect structure. In some realizations, the method also includes characterizing the interconnect structure based at least in part on the delay measurement.

Abstract: A chip design verifying and chip testing apparatus is provided including a storing means for storing an application program verifying an operation of a chip and testing the chip, the chip having a plurality of blocks, an I/O file, and a test vector; an interface means controlling a data transmission between the storing means and the chip, the interface means having a data applying means for applying the I/O file and/or the test vector outputted from the storing means and a data storing means for storing data outputted from the chip; and a computer including a CPU for performing and controlling the application program.

Abstract: A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e.g., an IEEE standard 1149.1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical.

Abstract: Adequately assigning features provided by the system to processing units having different architectures incorporated in a system LSI. An analysis unit is provided for counting the number of conditional branch statements and the number of loop control statements, the number of nestings of the conditional branch statements and the number of nestings of the loop control statements, and the number of functions required to generate the conditions of the conditional branch statements and the number of repetitions of loop control statements described in each function of a program describing system features in a high-level language.

Abstract: Computationally efficient methods and systems for optimizing an integrated circuit (IC) design by targeting only a limited subsection of buffer trees in the buffer system for optimization are provided. By making intelligent decisions about which buffer trees to optimize, greater gains in design efficiency (e.g., as measured by reduced delays and/or wire length) may be realized at greatly reduced computational times when compared to conventional techniques that attempt to optimize each buffer tree.

Abstract: In at least one hardware definition language (HDL) file, a design entity containing a functional portion of a digital system is specified. The design entity logically contains a plurality of configuration latches each having multiple different possible latch values. The latch values of the plurality of configuration latches collectively define at least a portion of a configuration of the functional portion of the digital system. With a statement in the at least one HDL file, a read-only Dial entity is associated with the plurality of configuration latches. The read-only Dial has at least one output and a mapping table indicating a mapping between each of a plurality of possible output values that can be present at the output and a respective corresponding setting of the read-only Dial. The setting of the read-only Dial indicates which of a plurality of different possible configurations is represented by the latch values of the plurality of configuration latches.

Abstract: A system and method facilitates the implementation of analog circuitry in electronic programmable devices. A user can specify user measurable parameters for analog features of the circuit, without requiring knowledge of the internal way in which those analog circuit are implemented in the programmable device to achieve desired properties of the analog parameters of interest. The implementation can be performed in different devices which may implement the analog circuit in vastly different ways.

Abstract: A technique for actively shielding a signal such that a signal driver of the signal only participates in discharge events is provided. Because the signal driver only participates in discharge events, the signal driver is non-interacting with respect to other driver devices. Shield wires are set such that an active transition on the signal causes a discharge of capacitance between the signal and the shield wires.

Abstract: A new method to optimize a signal routing in an integrated circuit is achieved. The method comprises providing a signal routing in an integrated circuit layout. The signal routing comprises a configuration of metal lines in a stack of metal levels. Each metal level is separated from an underlying substrate by dielectric material. A Joule heating estimate is calculated for the signal routing. The Joule heating estimate is compared to a standard value. The signal routing is updated if the Joule heating estimate exceeds the standard value. The updating comprises generating a new configuration of the metal lines in the metal levels. The new configuration reduces the Joule heating. The steps of calculating, comparing, and updating are repeated if the Joule heating estimate still exceeds the standard value. Joule heating is reduced by either routing on lower metal levels or by coupling the signal routing to a heat sink.

Abstract: One embodiment of the present invention provides a system that verifies whether a trace can be produced by a generator. A generator is defined as a finite state machine with a set of input and output signals. A trace is defined as a sequence of assignments of non-parametric input and output signals of the generator. The generator may contain parametric inputs to model non-determinism. The trace does not contain assignments of the parametric inputs. During operation, the system builds a data structure to determine if there exists a sequence of parametric input assignments that can match the non-parametric inputs and outputs of the generator with the ones specified in the trace.