Abstract: A scan diagnosis system for testing and diagnosing a device-under-test is disclosed. The system includes a semiconductor tester adapted for coupling to the device-under-test and operative to generate pattern signals in the ATE domain to test the device-under-test and produce test output data in the ATE domain. An ATPG diagnosis tool is operative to generate ATPG pattern data and ATPG results data in the ATPG domain. A translator serves to effect automatic correlation of data between the ATPG domain and the ATE domain to allow data communication between the tester and the tool.

Abstract: Methods, data processing systems, and program products are disclosed that support the definition and accessing of links indicating a relationship between configuration construct instances, such as Dial and Dial group instances, within a digital design. According to one method, first and second latches within the digital design are specified in at least one HDL statement within one or more HDL files representing the digital design. In the one or more HDL files, a first configuration construct instance referencing the first latch and a second configuration construct instance referencing the second latch are also defined. The first and second configuration construct instances provide interfaces through which values of the first and second latches can be accessed. In addition, a link indicating a relationship between the first and second configuration construct instances is also defined within the one or more HDL files.

Abstract: Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.

Abstract: Some embodiments of the invention provide a method of pre-computing routes for nets a region of a design layout. These routes are used by a router that uses a set of partitioning lines to partition the region into a plurality of sub-regions. For each particular set of potential sub-regions, the method initially identifies a set of routes that traverse the particular set of potential sub-regions. For each particular route identified for each particular set of sub-regions, the method then determines whether the particular route is stored in a storage structure. If not, the method stores the particular route in the storage structure.

Abstract: The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones.

Abstract: A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method and system, a user may access the server over the network and enter a request for a memory design. The front-end software process is then executed to automatically generate a netlist of a BIST from the user request. Thereafter, the back-end software process is executed to automatically generate a placement and route view of the BIST.

Abstract: Method and apparatus for phase-timing compensation is described. More particularly, a clock source and a clock sink of a path are identified for phase-timing compensation for a design. An absolute path slack is obtained, and phase offset of the clock source relative to the clock sink is determined. A normalizing factor responsive to the phase offset is generated. A normalized slack is computed using the absolute path slack and the normalizing factor.

Abstract: A system, method and software product determine detail of analysis in a circuit design. Pull-up driver transistors of at least one stage of the circuit design are identified. Pull-down driver transistors of the stage are identified. Configuration commands associated with control signals of the pull-up and pull-down driver transistors are processed to determine if the pull-up driver transistors and pull-down driver transistors are tied on or tied off. A determination is made whether the stage has drive fight and switching current. A detailed analysis is performed of the stage of the stage has drive fight or switching current.

Abstract: In accordance with the present invention there is provided a method for determining an optimized parameter for a circuit simulation. A circuit path for the simulation is determined, and maximum and minimum optimization parameters are decided. Next, the circuit path is simulated using the maximum optimization parameter. The circuit path is simulated using the minimum optimization parameter and a primary criteria parameter is also calculated. The simulations are compared to determine whether the same status (both succeed or both fail) is generated for both the minimum optimization parameter and the maximum optimization parameter. If the simulations do not indicate the same status, then the optimization parameter is recalculated and the circuit is simulated until the primary criteria parameter converges to a prescribed value.

Abstract: A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.

Abstract: A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the size of the circuit design to the minimum legal size. The scaling may be followed by application of minpert analysis to correct any errors introduced by the scaling. The resulting design is shrunk (or expanded) with all elements shrinking (or growing) together by the same factor, and with the relative relationships of elements maintained. In addition, the invention is operational in the presence of a positive cycle, can be run with scaling that freezes the sizes of any structure or ground rule, and can be applied to technology migration.

Abstract: A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a representation of the switching behavior which differentiates the time that circuits or transistors switch. One embodiment of the invention, utilizes a method such as, but not limited to, time resolved photon emission to observe transistor level switching activity in an integrated circuit (IC).

Abstract: A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure.

Abstract: A method and computer program are disclosed for reducing routing congestion in an integrated circuit design that include steps of: (a) receiving as input a design for an integrated circuit die having an inner metal layer and a top metal layer wherein the design includes electrical constraints of each of a plurality of I/O circuits in the integrated circuit die; (b) selecting a number of vias for a via array to form an electrical connection between the inner metal layer and the top metal layer of the integrated circuit die that connects a solder bump formed on the top metal layer to a corresponding one of the plurality of I/O circuits wherein the number of vias is selected to satisfy the electrical constraints of the corresponding one of the plurality of I/O circuits; and (c) generating as output the number of vias determined for the via array.

Abstract: Boolean circuits are designed with minimal depth by calculating the depth of an existing circuit. Those subtrees having a non-regular root cell (i.e., cells having other than one child or having a child of a type different from the cell) are balanced by constructing a new subtree. The cells are then iteratively transformed with parent and/or grandparent cells to reduce the depth of the circuit. The transformation may include balancing the subtree to make the parent cell the same type as the selected cell, or by creating a new cell as parent to the selected cell.

Abstract: Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of designing an integrated circuit includes several steps. In one step, a foundation block for the integrated circuit is specified, including specifying the locations of multiple androgynous interfaces in the integrated circuit. In another step, one or more component blocks to comprise the integrated circuit are identified for use. In another step, the component blocks to form a layout of the integrated circuit are positioned in a manner that minimizes connection distances between functional blocks and between functional blocks and the androgynous interfaces. In another step, the androgynous interfaces are set to perform as targets (slaves) or initiators (masters) based on the layout.

Abstract: Some embodiments of the invention provide a method of routing nets in a multi-layer integrated-circuit (“IC”) layout. For a particular net, the method specifies widths for routing the particular net in different directions on the same layer. It then defines a particular route for the particular net, where the route has different widths in the different directions on the same layer.

Abstract: A method of manufacturing a System In Package (SIP) or Integrated System in Board (ISB) circuit device in which a plurality of circuit elements are covered with and integrally supported by an insulating resin. A user terminal is connected with an ISB server and an ISB mounting factory through a communication network. Specifications to be satisfied by an ISB circuit device desired by a user, such as an external size and terminal information of the ISB and circuit diagram CAD data, for example, are input through the user terminal and transmitted to the ISB server. The ISB server in turn transmits information concerning the due date and cost of the ISB circuit device and also a reliability evaluation result to the user terminal. The ISB server also generates mask data for manufacturing the ISB circuit device based on the input specifications, and transmits the mask data to the ISB mounting factory.

Abstract: The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity correction, and then removed prior to taping a pattern onto the reticle. Design features can alternatively, or additionally, be introduced after optical proximity correction and asymmetrically relative to one or more parts of a reticle pattern. The introduced features can subsequently be taped to the reticle as part of the formation of the patterned reticle.

Abstract: A method is described that involves automatically generating a physical behavior curve from a process description; where, the process description describes a process. The method also involves automatically generating a device model for the process from the physical behavior curve; where, the device model is represented in geometric form. The method also involves attempting to automatically generate, with the device model and with a geometric optimization sequence, a circuit design for the process.