Abstract: A flip chip integrated circuit package which has a layer of nickel-boron (Ni--B) on the contact pads of the package substrate and a layer of nickel-phosphorus (Ni--P) on the pins of the substrate. A layer of gold is plated onto the layers of nickel. An integrated circuit with a plurality of solder bumps is placed onto the contact pads of the substrate. The package is heated to reflow the solder bumps, gold and nickel-boron into solder joints that attach the integrated circuit to the substrate. The package is then typically shipped and mounted to a printed circuit board by soldering the pins to the board.

Abstract: A semiconductor lead frame in which a semiconductor chip is mounted using an insulating adhesive film. The semiconductor lead frame includes an inner lead and a plating layer. The inner lead has a plating groove formed therein at an end portion of a surface opposite a surface to which the insulating adhesive film is attached. The plating layer rests on the plating groove such that an upper surface of the plating layer and the opposite surface of the inner lead are flush. Since the upper surfaces of the plating layer and the inner lead are flush, a pressing force by a heater is uniformly transmitted to a semiconductor chip, thereby improving adhesion reliability of the semiconductor chip.

Abstract: A resin sealed semiconductor device, wherein support pins uphold a pair of facing sides of the semiconductor chip. A projected portion is formed on the distal end portion of the support pin in proximate to the semiconductor chip. The projected portion is formed on both sides of the supporting members which respectively correspond to an upper side and a bottom side of the semiconductor chip in such a manner that when the projected portions are viewed from the upper side or bottom side of the semiconductor chip, they overlap with each other. All of the height of the projected portions are the same. The thickness of the resins formed on both opposite sides of the semiconductor chip is the same with each other, thus preventing the upward or downward displacement within the sealing resin of the semiconductor chip in a thin package.

Abstract: An FET isolated on either side by a trench. The FET has a dielectric layer in the isolating trench along at least one side. The dielectric layer which may be an ONO layer has an oxidation catalyst diffused into it. The oxidation catalyst may be potassium. A gate oxide along the side of the FET in close proximity to the ONO layer is thicker than gate oxide between both sides.

Abstract: A double tunnel junction is disclosed that can be used as a magnetic sensor or as random access memories. The preferred embodiment comprises three magnetic metal materials separated by two insulating layers. A current is passed through the first tunnel junction thereby developing a voltage in the second junction. The resistance of this device can be changed over a 100% when an external magnetic field of just a few gauss is applied.

Abstract: The resin-sealed semiconductor device of this invention includes: a first semiconductor chip having a plurality of terminals, a first surface on which the plurality of terminals are formed, and a second surface opposite to the first surface; a second semiconductor chip having a plurality of terminals, a first surface on which the plurality of terminals are formed, and a second surface opposite to the first surface; a third semiconductor chip having a plurality of terminals, a first surface on which the plurality of terminals are formed, and a second surface opposite to the first surface; and a lead frame having a plurality of leads connected with at least one of the plurality of terminals of the first semiconductor chip, at least one of the plurality of terminals of the second semiconductor chip, and at least one of the plurality of terminals of the third semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip are disposed so that the first surface of the first semiconductor

Abstract: A chip type electronic component is provided which includes a chip substrate having an opposite pair of end edges and an opposite pair of side edges between the pair of end edges. An opposite pair of first electrodes is formed in a layer on the chip substrate to extend from the end edges toward each other. Each first electrode has a narrower root portion closer to a corresponding end edge of the chip substrate and a wider head portion spaced from the corresponding end edge. An electronic element is formed in another layer on the chip substrate in electrical conduction with both of the first electrodes, and an insulating protective coating is formed on the chip substrate to entirely cover the electronic element together with the entire wider head portion of each electrode.

Abstract: A rectangular semiconductor chip is bonded onto a rectangular island at the center of a frame having a plurality of inner leads extending radially from the center. The chip has a plurality of pads adapted to be connected by wire bonding to corresponding ones of the inner leads. The pads are disposed sequentially along at least one side of the rectangular chip. Separations between mutually adjacent pairs of these pads along the side of the chip are smaller in the center part than in the end parts of the side such that the pads can be disposed closer together while preventing interference between mutually adjacent pairs of the bonding wires.

Abstract: A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Abstract: A microelectronic package suitable for high-frequency microelectronic devices includes a base which is at least partially conductive attached to an RF substrate with a cavity formed at its center and a pattern of conductive paths for providing interconnection from the inside to the outside of the package. The base may be metal or ceramic with a metal layer deposited thereon. A sealing cap is attached to the RF substrate by a non-conductive adhesive, such as a polymer adhesive or low temperature seal glass, to seal the package once the microelectronic device has been mounted inside.

Abstract: An electronic device assembly includes a large-scale-integrated circuit (LSI) chip having center and peripheral portions. A circuit and terminals are formed in the center in and peripheral portions, respectively. A carrier substrate is attached to the center portion of the LSI chip. The carrier substrate has center and peripheral portions. Bumps and terminals are provided in the center and peripheral portions of the carrier substrate. Wires connect the terminals of the LSI chip and the carrier substrate. The carrier substrate is mounted on a substrate via the bumps. The thermal expansion coefficient of the carrier substrate is between those of the LSI chip and the substrate.

Abstract: A power semiconductor module including a housing that has a housing wall and a base on which the housing is disposed. A number of semiconductor components are disposed on the base. A terminal element includes a portion contained in the housing wall, at least two terminal pins projecting from the housing wall, and an exposed lower part projecting into the housing from the housing wall. The portion of the terminal element contained in the wall and the lower part of the terminal element have a cross-section that is larger than the sum of the cross-sections of each of the terminal pins. The lower part of the terminal element is electrically connected to at least one of the semiconductor components.

Abstract: A semiconductor device includes a semiconductor chip; leads including first inner leads and second inner leads extending substantially radially from a central point of the semiconductor chip; electrical conductors electrically connecting the semiconductor chip to the lead frame; and an encapsulating resin encapsulating the semiconductor chip, the electrical conductors, and the inner leads, Each of the first inner leads has a first inner end located proximate the central point and each of the second inner leads has a second inner end located farther from the central point than the first inner ends. The first and second inner leads are alternatingly arranged. Thus, at least some of the inner leads extend under the semiconductor chip, providing heat conducting paths. The lead frame includes a frame and leads supported by the frame and including first inner leads and second inner leads extending substantially radially toward a central point of the frame.

Abstract: A semiconductor device has a semiconductor chip which is divided into a plurality of separate regions. In each of these regions, there are provided a plurality of common discharge lines which are independent from one another, a plurality of first bonding pads which are connected directly to the respective common discharge lines, a plurality of second bonding pads which are not connected directly to the common discharge lines, a plurality of protective elements which are connected between the second bonding pads and the common discharge lines, and an inner lead for discharging which is directly connected to the first bonding pads and is bonded to a surface of the semiconductor chip. In all embodiments of the invention. More than one common discharge line is provided. This arrangement permits the reduction of the chip area thus enhancing design freedom and improving electrostatic breakdown characteristics.

Abstract: Method and apparatus for reducing current leakage between overlapping conductive structures in a multi-layered integrated circuit device such as a thin film capacitor is described. A conductive structure operating as a raised lower electrode is preferably fashioned by step-like erosion using a photolithographic techniques atop a dielectric substrate. In accordance with this invention, the dielectric substrate itself is allowed to erode as well to space the conductive structure away from the problemmatic inner corners of the step. By so distancing such conductive structures, like electrodes, from these inside corners, even conventional deposition techniques can be used to fabricate a capacitive device of operational tolerance suitable for DRAM application without risk of unwanted electrode current leakage and possible shorting.

Abstract: An electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density.

Abstract: A non-volatile memory device in which gate electrodes are formed on an upper surface and a lower surface of the channel via insulating layers, respectively, one of them is used as a read electrode and the other is used as a write electrode, whereby, at a read operation the reading is carried out without exerting an influence upon stored charges stored at the time of writing. Particularly, it has a structure in which a source and drain region of the non-volatile semiconductor memory device in formed in the semiconductor layer formed on the insulating layer and, at the same time, one of the read electrode and write electrode is buried in the insulating layer.

Abstract: A color linear charge coupled device for an image pickup apparatus includes red, green, and blue photo diode arrays. First, second, third and fourth transfer gates formed in the device move signal charges generated at the photo diode arrays toward first, second and third horizontal charge coupled device (HCCD) shift registers. By controlling the transfer gates, the red and green signal charges are first transferred to their HCCD shift registers. The blue signal charge is then transferred to its HCCD shift register. Only three HCCD shift registers are required, thus, the device dimension and configuration is considerably simplified compared to prior art configurations. Also, the color resolution of the device is greatly improved because the distance between the respective photo diode arrays is substantially decreased.

Abstract: A device having a switch comprises a chromium layer and an adjacent semiconductor layer. The fraction of voids in the chromium layer is less than 10%, preferably less than 2%. The chromium layer in the device comprises traces of neon with a concentration of less than 0.1 at. %.Chromium layers are deposited on a substrate by means of a sputter deposition process. By using neon as the working gas at pressures of less than 1 Pa, preferably in the range from 0.2 Pa to 0.5 Pa, the sputter-deposited chromium layers are substantially free of internal stress and have a density which is approximately equal to that of bulk chromium.

Abstract: A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.