Abstract: A semiconductor device is formed from a die and a lead frame having one or more bus bars. Portions of the bus bars are overlain with an electrically insulative material while leaving bonding areas unobstructed, whereby bond wires which span the bus bar(s) may be bonded with a shorter wire and a lower loop, without the danger of shorting to the bus bar(s). The incidence of harmful wire sweep in the encapsulation step is also reduced.

Abstract: Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum.

Abstract: An improved package structure for integrated-circuit chips is disclosed. In accordance with a preferred embodiment of the present invention, the integrated-circuit packaged structure comprises a wiring substrate, an integrated-circuit chip, and a heat spreader. The integrated-circuit chip has a first surface and a second surface, wherein the first surface is electrically and mechanically connected to the wiring substrate via a first set of solder joints. The heat spreader is connected to the second surface of the integrated-circuit chip via a second set of solder joints. The heat spreader includes an adhesion-promotion layer on top of a silicon layer, such that heat generated from the integrated-circuit chip can be efficiently transmitted to and subsequently dissipated by the heat spreader.

Abstract: The present invention provides a digital vertical multi-valued logic device including a substrate defining a horizontal plane and a vertical direction normal to the horizontal plane, a substantially vertical conductive gate structure disposed above the substrate, source and drain regions, a channel region positioned between the source and drain region and adjacent to the gate structure, the channel region including at least a first and second tunnel barrier forming a quantum well structure. The quantum well acts to incorporate an artificial bandstructure into the present invention modifying device performance. By introducing quantum wells into the device structure, quantum-mechanically defined drain voltage levels are introduced in the MOS transistors at which no current flows, creating stable intermediate logic levels.

Abstract: A semiconductor chip assembly with a compliant layer overlying the chip and a flexible dielectric layer overlying the compliant layer. Connecting terminals are provided on the dielectric layer for connection to a larger substrate. The connecting terminals are moveable in vertical directions toward the chip. Bonding terminals, electrically connected to the connecting terminals, are also provided on the top layer. A reinforcing element resists vertical movement of the bonding terminals, and thereby facilitates connection of leads between the bonding terminals and the chip.

Abstract: A QVDMOS array 10 has QVDMOS devices with a silicide contact 42 to source 35 and body tie 36. The body tie 36 is enclosed by the source at the surface and extends beneath but not beyond the annular source 35. The QVDMOS is formed during a number of process steps that simultaneously form regions in NMOS, PMOS and bipolar devices.

Abstract: Semiconductor devices suited for high-density packaging, a method of connecting such semiconductor devices, and connectors for connecting such semiconductor devices. Each semiconductor device 10 includes a plurality of exposed terminals 13 arranged two-dimensionally on opposite surfaces thereof. Each connector 30 includes a plurality of connecting pins projecting from opposite surfaces thereof and arranged two-dimensionally in a corresponding relationship to the exposed terminals 13. Each end connector 33 includes connecting pins 34 likewise arranged two-dimensionally on an inward surface thereof. These connectors 30 and 33 are used to sandwich a plurality of semiconductor devices 10 to form a package. The exposed terminals 13 of the semiconductor devices 10 are electrically connected through the connecting pins of the connectors 30 and 33.

Abstract: A nitride semiconductor light-emitting device has an active layer of a single-quantum well structure or multi-quantum well made of a nitride semiconductor containing indium and gallium. A first p-type clad layer made of a p-type nitride semiconductor containing aluminum and gallium is provided in contact with one surface of the active layer. A second p-type clad layer made of a p-type nitride semiconductor containing aluminum and gallium is provided on the first p-type clad layer. The second p-type clad layer has a larger band gap than that of the first p-type clad layer. An n-type semiconductor layer is provided in contact with the other surface of the active layer.

Abstract: An integrated structure active clamp for the protection of a power device against overvoltages includes a plurality of serially connected diodes, each having a first and a second electrode, obtained in a lightly doped epitaxial layer of a first conductivity type in which the power device is also obtained; a first diode of said plurality of diodes has the first electrode connected to a gate layer of the power device and the second electrode connected to the second electrode of at least one second diode of the plurality whose first electrode is connected to a drain region of the power device; said first diode has its first electrode comprising a heavily doped contact region of the first conductivity type included in a lightly doped epitaxial layer region of the first conductivity type which is isolated from said lightly doped epitaxial layer by a buried region of a second conductivity type and by a heavily doped annular region of the second conductivity type extending from a semiconductor top surface to said bu

Abstract: In accordance with the invention, integrated circuit dies may be packaged in a plastic package employing an area area array technology such as a conductive ball grid array, column grid array or pin grid array. One aspect of the invention is an integrated circuit package(10) which includes an electronic circuit enclosed by a plastic body (12, 14). The molded plastic body has a first major surface opposing a second major surface. The first major surface of integrated circuit (10) has a plurality of openings therein. One of a plurality of conductive pads (18) is adjacent to each one of the openings and is electrically connected to the electronic circuit. Each of a plurality of conductors (20) is electrically connected to one of the pads (18) and protrudes from one of the openings (22).

Abstract: An electronic package which has a plurality of stacked integrated circuit dies. The package includes a first die that is mounted to a die paddle of a lead frame. The first die is also connected to the leads of the lead frame by bond wires. A second die is mounted to the top surface of the first die and electrically connected to the first die with bond wires. The first die, second die and die paddle are all enclosed by a package.

Abstract: A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with the semiconductor device may be effected. The array of logic gates is linearly continuous and is unbounded along at least a first axis through to boundaries imposed an edge of the semiconductor wafer. The arrays of I/O circuit devices and connector pads are disposed adjacent, and in one embodiment parallel, to the array of logic gates. Integrated circuit structures including a customized number of individual logic gate elements may be easily provided by cutting a selected length from the strip-like portion of the array of logic gates. Requisite connector pad and I/O circuit features are provided by the adjacent arrays of I/O circuit devices and the adjacent array of connector pads.

Abstract: An impact load effected on the single body of an acceleration sensor device is absorbed with a relatively simple construction, thereby protecting a semiconductor sensor element provided in the sensor. The acceleration sensor device comprises a semiconductor sensor element 2 which can sense an acceleration in a direction perpendicular to its principal plane, a base plate 3 which supports the sensor element 2, a package 11 which supports the base plate 3 and encloses the base plate 3 and the sensor element 2, a frame 12 which has a plurality of leg sections 12d protruding from a bottom plane of the package 11 and is fixed on the package 11, and a cap-shaped resin cover 13 which has a roof section 13a opposite to an upper surface of the package 11 or the frame 12 and covers the package 11 from above as fixed on the package 11, and a side wall section 13b of the cover 13 extends at least to a position corresponding to a place where the sensor element 2 is arranged.

Abstract: A high frequency semiconductor component (10) includes a first substrate (12) having a first surface (13) opposite a second surface (14), a first electrically conductive layer (16) supported by the first surface (13) of the first substrate (12), a second electrically conductive layer (17) supported by the second surface (14) of the first substrate (12) wherein the second electrically conductive layer (17) is electrically coupled to the first electrically conductive layer (16), a second substrate (19) having a first surface (20) and a second surface (21), a third electrically conductive layer (22) supported by the first surface (20) of the second substrate (19), and an electrically insulating layer (23) between the second and third electrically conductive layers (17, 22) wherein the second and third electrically conductive layers (17, 22) are electrically coupled together through the electrically insulating layer (23).

Abstract: In a sub-micron line width process, a first layer of polysilicon 13 is patterned into lines 1,2 spaced a predetermined distance. An oxide layer 11 is deposited. A second layer of polysilicon 14 is deposited on the insulating layer. A gate contact 19 or emitter contact 35 is formed from the second polysilicon layer 14. The gate 19 or emitter 35 is spaced from the lines 1,2 a distance approximately equal to the thickness of the second polysilicon layer 14.

Abstract: A hermetically sealed microelectronic package that uses a thermal barrier or interposer between a cover and an aluminum nitride substrate. A solder interface is disposed on an aluminum nitride substrate, and the thermal barrier is disposed on the solder interface. The cover is attached to the solder interface using a solder seal that solders the cover to the interposer to produce a hermetically sealed package. The thermal barrier or interposer permits low cost, low temperature soldering of metal covers to metallized aluminum nitride substrate and is compatible with volume production processing.

Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N.sup.+ type diffusion layer, N.sup.- type epitaxial layer, P.sup.- type epitaxial layer, P.sup.+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P.sup.- epitaxial layer, the efficiency in density control at the time of P.sup.- type epitaxial growth can be improved.

Abstract: A photoelectric conversion device including: a photoelectric conversion portion having a light absorbing layer disposed between charge injection inhibition layers and having a predetermined forbidden band width Eg.sub.1, and a carrier multiplication portion including a single or a plurality of inclined band gap layers, the inclined band gap layer including a minimum forbidden band width Eg.sub.2 and a maximum forbidden band width Eg.sub.3 which are disposed to be in contact with each other to form a hetero junction and having, at the two ends thereof, forbidden band widths Eg.sub.4 which holds a relationship Eg.sub.2 <Eg.sub.4 <Eg.sub.3 in such a manner that the forbidden band width is continuously changed from the two forbidden band widths Eg.sub.2 and Eg.sub.3 to the forbidden band width Eg.sub.4, and the energy step in a conductive band of the hetero junction portion is larger than the energy step in a valence electron band, wherein at least the minimum forbidden band width Eg.sub.

Abstract: An integrated circuit photodetector includes a transimpedance amplifier including a differential amplifier stage with PNP emitter-coupled transistors and a PNP input transistor which are biased only by base currents of the emitter-coupled transistors, to achieve low input bias current. Low noise operation is achieved by bypass capacitors coupled between the bases and emitters of the input transistors, respectively. A constant current source supplies a current which develops a small pedestal voltage across a resistor to bias the non-inverting input of the transimpedance amplifier so as to avoid nonlinear amplification of low level light signals. A positively biased N-type guard tub surrounds the photodetector, which is formed in a junction-isolated N region on a P substrate, to collect electrons generated in the substrate by deep-penetrating IR light to prevent them from causing amplification errors.

Abstract: A surface field effect integrated transistor has the surface of the silicon in the source and drain areas lowered by 50-500 nm in respect to the surface of the silicon underneath the gate electrode by etching the silicon substrate before forming the source and drain junctions.The transistor is sturdy and reliable because of the backing-off of the multiplication zone of the charge carriers from the gate oxide by a distance greater than several times the mean free path of hot carriers, thus markedly reducing the number of hot carriers available for injection in the gate oxide.The modified fabrication steps are readily integrable in a normal CMOS fabrication process.