Patents Examined by Mahshid D. Saadat
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Patent number: 5789807Abstract: A specific structure which improves the decoupling capacitance for the power conductors in parallel metal layers of a semiconductor device. The power conductors are arranged so that conductors vertically adjacent to each other in the two outer of three metal layers are never connected to the same supply voltage terminal, but rather to opposing terminals. To improve current carrying capacity and reduce area, a power conductor in one outer plane is connected to a power conductor in the other outer plane which is displaced vertically and laterally from the first power conductor. The connection is made through special stitch conductors in the intervening plane. The resulting structure improves power supply decoupling for the finished device by providing significantly greater capacitance associated with the power distribution system of the chip.Type: GrantFiled: November 26, 1997Date of Patent: August 4, 1998Assignee: International Business Machines CorporationInventor: Anthony Correale, Jr.
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Patent number: 5789774Abstract: The leakage current at the silicon-to-silicon dioxide interfaces of an active pixel sensor cell is substantially reduced by eliminating field oxide from the cell, and by insuring that, during integration, every surface region of the cell that is not heavily doped is either biased into accumulation or biased into inversion. Each of these states, in turn, substantially limits the number of electrons from thermally-generated electron-hole pairs at the surface that can contribute to the leakage current.Type: GrantFiled: May 14, 1997Date of Patent: August 4, 1998Assignee: Foveonics, Inc.Inventor: Richard Billings Merrill
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Patent number: 5789820Abstract: In a method for manufacturing a heat radiating resin-molded semiconductor device, a protrusion is formed on a side peripheral surface of a semiconductor chip, and the semiconductor chip is sealed with resin, so that spreading of the resin toward a back surface of the semiconductor chip is prevented by the protrusion. Also, a heat radiator is mounted on a back surface of the semiconductor chip.Type: GrantFiled: February 28, 1997Date of Patent: August 4, 1998Assignee: NEC CorporationInventor: Chikara Yamashita
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Patent number: 5786621Abstract: A novel apparatus and technique or characterizing materials at submicron scale and for characterizing micromechanical devices integrates test specimens with the testing device. The test specimen is a micromechanical structure made of the material to be characterized or may be a device under evaluation. A microloading instrument is a microelectromechanical structure incorporating a stable, planar frame to which is connected a multiplicity of comb-type capacitive actuators. A variable drive voltage applied across the actuator plates selectively moves the frame structure along a longitudinal axis in a controlled fashion. The frame is mounted to a fixed substrate by means of laterally extending spring arms which position the capacitor plates and guide the motion of the frame along the longitudinal axis. The micro loading instrument is calibrated by buckling a long slender beam cofabricated with the instrument.Type: GrantFiled: June 21, 1996Date of Patent: July 28, 1998Assignee: Cornell Research Foundation, Inc.Inventors: Muhammed T. A. Saif, Noel C. MacDonald
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Patent number: 5786635Abstract: An electronic package wherein an electronic device (e.g., chip) on a circuitized substrate of the package is thermally coupled to a heatsink in a separable manner using a plurality of compressible, thermally conductive members (e.g., solder balls). These members are compressed and permanently deformed as part of the thermal coupling.Type: GrantFiled: December 16, 1996Date of Patent: July 28, 1998Assignee: International Business Machines CorporationInventors: David James Alcoe, Sanjeev Balwant Sathe
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Patent number: 5786622Abstract: A novel ring shaped emitter structure with an extrinsic base and base contact in the central portion of the ring is described. This structural configuration is useful for improving the performance of bipolar transistors used in BiCMOS integrated circuits with only minimal changes to conventional CMOS processing technology. A single additional mask is required to form the intrinsic base region of the transistor. The emitter is diffused from a polysilicon layer which also serves as the emitter contact. The polysilicon layer overlies a perimeter portion of an active region defined by an opening in a field oxide and rises up over the field oxide itself. The active emitter region then forms a ring along the perimeter of the active region. The extrinsic base is formed through an opening within the polysilicon layer representing a central portion of the active region.Type: GrantFiled: May 16, 1997Date of Patent: July 28, 1998Assignee: TriTech Microelectronics International Ltd.Inventor: Hannu O. Ronkainen
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Patent number: 5786623Abstract: The dynamic range is increased and the noise level is reduced in a bipolar-based active pixel sensor cell with a capacitively coupled base region by forming the capacitor over a portion of the base region and the field oxide region of the cell. In addition, the noise levels are also reduced by heavily-doping the material which forms a portion of the bottom plate of the capacitor with the same conductivity type as the base region of the cell, and by placing the material which forms the portion of the bottom plate in direct contact with the base region.Type: GrantFiled: October 22, 1996Date of Patent: July 28, 1998Assignee: Foveonics, Inc.Inventors: Albert Bergemont, Min-hwa Chi
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Patent number: 5786634Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces; a function element layer having heating element portions generating heat during operation, disposed on the first main surface that is thinned; and a plated heat sink of a heat conductive material, having a thickness equal to or greater than that of the semiconductor substrate, disposed on a circumferential region of the second main surface at the perimeter of the semiconductor substrate inward, on main heat generating regions of the second main surface including regions opposite the heating element portions, and on supporting regions of the second main surface connecting the circumferential region to the main heat generating regions. The semiconductor device maintains the heat generating function and the handling performance of the plated heat sink, reduces internal stress during plating and repeated stress produced by heat cycles during fabricating processes, and lessens chip breakage and plating peeling.Type: GrantFiled: December 29, 1996Date of Patent: July 28, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kiyoshi Nishikawa, Mitsunori Nakatani, Katsuya Kosaki
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Patent number: 5786639Abstract: A wiring member comprising a first electrode portion electrically connected with an electrode formed on a surface of a semiconductor element, a second electrode portion electrically connected with an electrode formed on an external circuit, and a wiring portion which connects the first electrode portion with the second electrode portion. The first electrode portion, the second electrode portion and the wiring portion are formed of a plate-shaped conductive body, and a thickness of the wiring portion is made not more than half as thick as the first electrode portion or the second electrode portion. Fine wiring can be achieved by making the lead as a wiring member for electrically connecting the semiconductor element electrodes with the external electrodes of the semiconductor device not more than half as thick as the lead frame material at need.Type: GrantFiled: July 3, 1997Date of Patent: July 28, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yoshiharu Takahashi
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Patent number: 5786629Abstract: This invention relates to a three-dimensional package or module which includes a large number of subassemblies or fillo-leafs arranged in a stack. The subassemblies which carry integrated circuits are bonded at one of their edges so they extend cantilever fashion into a fluid coolant. Each fillo-leaf includes a heat dissipating element and one is spaced from another by an ultraviolet light cured material which is in registry with a transparent edge portion of each fillo-leaf. The transparent edge portions are formed, on the wafer level, and used, on the wafer level to cure the U.V. curable material.Pairs of encoder lines which are used to provide a unique address extend from the edge of each fillo-leaf to an associated comparator. When stacks of fillo-leafs are diced from a stack of wafers, the pairs of encoder lines are encoded by shorting or not shorting the exposed ends of encoder lines which extend from the edge of each fillo-leaf.Type: GrantFiled: April 3, 1996Date of Patent: July 28, 1998Assignee: Reveo, Inc.Inventor: Sadeg Mustafa Faris
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Patent number: 5783857Abstract: An IC package appropriate for microwave devices, integrated circuits, multichip modules, and hybrid circuit assemblies and power devices comprises an outer interconnect (2) and an inner interconnect (3). Lead lines (8) on an outer interconnect (2) are in electric engagement with respective access lines (13) on an inner interconnect (3). Contacts (21) of an IC are electrically interconnected with the access lines (13) on the inner interconnect (3). A package according to the teachings of the present invention provides for efficient heat dissipation from the package interior and an efficient electrical transition from the interior of a package.Type: GrantFiled: July 25, 1996Date of Patent: July 21, 1998Assignee: The Whitaker CorporationInventors: Bernhard Alphonso Ziegner, Robert John Sletten
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Patent number: 5783866Abstract: A panel of, for example, bismaleimide triazine (BT) or ceramic (Al.sub.2 O.sub.3) is chosen in size to be substantially filled with and taken up by end-result ball grid array (BGA) devices. The end-result devices are positioned closely together and take up substantially the entire area of the initial panel. Structural weakening is provided at appropriate places in the panel to allow the devices to be readily singulated.Type: GrantFiled: May 17, 1996Date of Patent: July 21, 1998Assignee: National Semiconductor CorporationInventors: Shaw Wei Lee, Hem P. Takiar, Ranjan J. Mathew, Hee Jhin Kim
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Patent number: 5783861Abstract: A semiconductor package comprises at least one semiconductor chip; a lead frame having a chip paddle supporting a semiconductor chip, a plurality of inner leads wire-bonded to the chip and a plurality of outer lead extended from the inner leads; and a plastic molding compound sealing the chip and the inner lead of the lead frame, wherein the outer leads of the lead frame being arranged within an area of a bottom surface of the plastic molding compound.A lead frame for use in the semiconductor package comprises a plurality of inner leads to be connected respectively to pads of a semiconductor chip; a plurality of outer leads extended from the inner lead and to be connected to other circuit, and the outer leads being bent to downward from an internal end of the inner lead.Type: GrantFiled: March 10, 1997Date of Patent: July 21, 1998Assignee: LG Semicon Co., Ltd.Inventor: Deog Soo Son
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Patent number: 5783867Abstract: In a method for reversible assembly of a semiconductor electronic flip-chip device to an electrical interconnecting substrate, a filled thermoplastic adhesive is interposed between an active face of the flip-chip device and a bond site on the substrate. Electrical connection is established between the flip-chip device and the substrate and, generally simultaneously, adhesive bonding between them is established via viscous flow of the filled thermoplastic adhesive above its glass transition temperature, followed by cooling of the adhesive. The adhesive can be reheated to free the flip-chip device of its adhesive bond to the substrate. The filled thermoplastic adhesive includes a low expansion filler in a binder matrix. In accordance with one aspect of the invention, the binder matrix is poly(aryl ether ketone) having the chemical formula ##STR1## where n is from 5 to 150 and R is selected from suitable divalent moieties.Type: GrantFiled: November 6, 1995Date of Patent: July 21, 1998Assignee: Ford Motor CompanyInventors: Robert Edward Belke, Bethany Walles, Michael G. Todd, Brian J. Hayden
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Patent number: 5780933Abstract: A one-sided sealed type semiconductor device comprising a substrate proper for a one-sided resin mold provided on the first main surface thereof with a wiring circuit including connection parts for semiconductor elements and on the second main surface thereof with flat type external connection terminals led out thereon via a through hole, semiconductor elements set in place and packaged in predetermined areas of the first main surface of the substrate proper, a transfer mold resin layer for sealing solely the surface having the semiconductor elements packaged thereon, and a metallic layer formed on the first main surface independently of wiring circuit and outside the area having the wiring circuit.Type: GrantFiled: May 10, 1996Date of Patent: July 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Jun Ohmori, Hiroshi Iwasaki, Takanori Jin
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Patent number: 5780910Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.Type: GrantFiled: July 17, 1996Date of Patent: July 14, 1998Assignee: Hitachi, Ltd.Inventors: Naotaka Hashimoto, Yutaka Hoshino, Shuji Ikeda
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Patent number: 5780871Abstract: This invention is related to an active matrix liquid crystal display (AMLCD) having a high pixel aperture ratio. The display has an increased pixel aperture ratio because the pixel electrodes are formed over the insulating layer so as to overlap portions of the array address lines. Both the manufacturability and capacitive cross-talk of the TFT-based device are improved due to the use of a photo-imageable insulating layer between the pixel electrodes and the address lines.Type: GrantFiled: April 2, 1997Date of Patent: July 14, 1998Assignee: OIS Optical Imaging Systems, Inc.Inventors: Willem den Boer, John Z. Z. Zhong, Tieer Gu
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Patent number: 5780913Abstract: When light is incident on the photoelectric surface of this electron tube, photoelectrons are emitted. These photoelectrons are accelerated and incident on an electron beam irradiation diode. A reverse voltage of about 100 V is applied to the electron beam irradiation diode to form a depletion region almost throughout an anode layer and near the p-n junction interface of a silicon substrate. The incident accelerated electrons release a kinetic energy in a heavily doped p-type layer having an electron incidence surface and the depleted anode layer to form electron-hole pairs. In this case, since the heavily doped p-type layer having the electron incidence surface is very thin, the energy is hardly released in this layer, and almost all energy is released in the depletion region. Signal charges extracted from the electron-hole pairs formed upon releasing the energy are output as a signal from two electrodes.Type: GrantFiled: October 27, 1997Date of Patent: July 14, 1998Assignee: Hamamatsu Photonics K.K.Inventors: Masaharu Muramatsu, Motohiro Suyama, Koei Yamamoto
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Patent number: 5780927Abstract: A semiconductor device includes a heat radiator having a convex portion. A reinforcement plate having a thermal conductivity is soldered on a portion of the convex portion of the heat radiator by a solder having a Young's modulus lower than a silver copper solder and a melting point lower than the silver copper solder. A semiconductor element soldered on the reinforcement plate by the solder.Type: GrantFiled: April 9, 1997Date of Patent: July 14, 1998Assignee: NEC CorporationInventor: Yukio Nomura
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Patent number: 5780928Abstract: An electronic system having improved thermal transfer from a semiconductor die in a semiconductor device assembly (package) by at least partially filling a cavity in the package with a thermally conductive fluid, immersing a heat collecting portion of a heat pipe assembly into the fluid, and sealing the cavity. In order that the thermally conductive fluid does not chemically attack the die or its electrical connections, the die and connections can be completely covered with an encapsulating coating of an inorganic dielectric material, such as silicon dioxide, by any of a variety of techniques. The heat pipe provides highly efficient heat transfer from within the package to an external heat sink by means of an evaporation-condensation cooling cycle. The optional dielectric coating over the die permits selection of the thermally conductive fluid from a wider range of fluids by isolating the die and its electrical connections from direct contact with the fluid.Type: GrantFiled: April 9, 1996Date of Patent: July 14, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Mark R. Schneider, Nicholas F. Pasch