Abstract: The present invention discloses a MOSFET power IC device formed in a semiconductor chip including a source contact area which is provided for connecting to a lead-frame via a several of lead-wires. The power IC device includes many lead-wire contact points on the source contact area for securely attaching the lead wires onto the source contact area. These lead-wire contact points are uniformly distributed substantially over the source contact area thus the spread resistance is reduced whereby the device on-resistance and device performance may be improved.

Abstract: A semiconductor lead frame having an improved structure formed of plated layers is provided. The semiconductor lead frame has the structure of multi-plated layers in which a Ni plated layer, a Pd strike plated layer, and a Pd--X alloy plated layer are deposited on a substrate in the described order. In such a multi-plated layer structure, the Pd strike plated layer covers the porous surface of the Ni plated layer and decreases the surface roughness. Since the thickness of the outer Pd--X alloy plated layer can be maintained uniform due to the Pd strike plated layer, corrosion durability and bonding characteristics are enhanced, thus minimizing the generation and progress of cracks.

Abstract: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the semiconductor light-emitting element, the bonding wire, and the upper end of the leads, provided with a non-circular lateral cross-sectional surface structure with a long axis and a short axis. In the device, when observed along a direction in which the plurality of light-emitting devices are mounted on a same lead frame, a curvature of the lateral direction of said envelope is smaller than a curvature of the vertical direction of said envelope.

Abstract: A semiconductor device includes a first metal film formed on a semiconductor substrate, a second metal film formed on the first metal film and containing silver as a main component, and a protective film containing a metal element of the first metal film and covering at least the upper surface of the second metal film. The protective film is formed by annealing in an atmosphere containing a predetermined element. That is, the metal element of the first metal film is diffused into the second metal film and reacts with the predetermined element in the atmosphere on the surface of the second metal film, thereby forming the protective film. Aggregation of silver is prevented in the presence of the protective film.

Abstract: A highly reliable semiconductor device having superior flatness and highly precise pattern is obtained. A first metal interconnection 7a is formed on a semiconductor substrate 1. An interlayer insulating film 8a is provided on semiconductor substrate 1 to cover the first metal interconnection 7a. A second metal interconnection 7b is provided on the interlayer insulating film 8a. The interlayer insulating film 8a includes a first silicon oxide film 107a provided on semiconductor substrate 1 to cover the first metal interconnection 7a, and a second silicon oxide film 108a provided to fill concave portions at the surface of the first silicon oxide film 107a. Height of the interlayer insulating film 8a from the surface of the semiconductor substrate 1 is made uniform entirely over one chip.

Abstract: There is provided a lead frame including an outer frame, a die pad on which a semiconductor device is to be mounted, a plurality of outer leads extending from the outer frame to the die pad, a dam bar connected at opposite ends thereof to the outer frame for connecting the outer leads to one another for prevention of resin overflow, and a support lead extending obliquely to the dam bar for connecting the die pad to the outer frame. The outer frame is formed beyond an end of the dam bar with an opening extending in a direction making an angle with a direction in which the dam bar longitudinally extends so that there is formed an elastically deformable portion between the opening and an end of the dam bar, the opening having a length covering at least a width of the dam bar.

Abstract: A liquid cooling system contained completely on a circuit board assembly. The liquid cooling system uses microchannels etched within the circuit board, those microchannels being filled with electrically conductive fluid that is pumped by a non-mechanical, magnetic pump. The pump can be separate from the device on the circuit board which is to be cooled or it can be integrated with the device that is to be cooled. In the latter circumstance, the same current which flows through the electronic device is the current which generates the Lorentz force that pumps the electrically conductive fluid through the microchannel.

Abstract: The size reduction on a longer side of a semiconductor apparatus mounted on a TAB mounting package is accomplished by slits 105' that are in contact with left and right edge portions of a potting resin 102 and that are longer than sides in the vertical direction of a base film 104. In addition, the size reduction in the vertical direction is accomplished by a structure of which an edge portion in an output outer lead portion 107 extends to the inside of a mounting region 402 of an IC chip 303 (namely, a portion below the IC chip 303) and this portion is connected to the outside of the semiconductor apparatus.

Abstract: A semiconductor light emitting device has a structure of stacked semiconductor layers including a double hetero junction, and a electrode having a plurality of stacked metal layers exhibiting a light transmitting property and an oxygen rich layer exhibiting the light transmitting property and interposed between said metal layers. The oxygen rich layer is preferably oxide layer. Such structure exhibits high light emission.

Abstract: The dynamic range is increased and the noise level is reduced in a bipolar-based active pixel sensor cell with a capacitively coupled base region by forming the capacitor over a portion of the base region and the field oxide region of the cell. In addition, the noise levels are also reduced by heavily-doping the material which forms a portion of the bottom plate of the capacitor with the same conductivity type as the base region of the cell, and by placing the material which forms the portion of the bottom plate in direct contact with the base region.

Abstract: Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets.

Abstract: A semiconductor device has a semiconductor chip with a plurality of pads, an inner lead which is connected to a plurality of pads by a plurality of bonding wires and which has a broken part portion, and a bonding wire which electrically connects broken ends of the broken portion of the inner lead and which has a fusing current smaller than that of the inner lead.

Abstract: A semiconductor device includes a package having opposing surfaces, a first terminal for an outer connection supported by said package and electronic components supported by said package, and the opposing surfaces of the package having slits so that a shape of the package can be changed in a mounted state. Therefore, stress applied to soldered junctions of the first and second terminals is decreased.

Abstract: A method and structure is given for flip-chip mounting an integrated circuit on a substrate. An embodiment of the present invention is a GaAs die flip-chip 14 mounted to a silicon semiconductor 10 which has additional processing circuitry. The flip-chip bond uses an alloy metal film, preferably a thin film of AuGe 38, 40. The invention gives a high temperature bond which is suitable for subsequent high temperature processes to be performed on the flip-chip mounted combination. The bond may also include a diffusion barrier 36 which provides a short circuit free LED contact. A preferred embodiment introduces a microchip chemical sensor by integrating a GaAs LED 14 with a polyimide waveguide 56 and a silicon photosensor 16 on the same chip.

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

Abstract: A flat-panel field emission display comprises a luminescent faceplate, a rigid backplate, and an interposed or sandwiched emitter or cathode plate. A dielectric connector ridge is screen-printed over the faceplate's rear surface. Upper and lower level conductors are then screen printed over the faceplate. The lower-level conductors are applied directly on the faceplate rear surface. The upper-level conductors are applied atop the connector ridge. A plurality of bond wire interconnections extend between individual screen-printed conductors of the upper and lower levels. The bond wire interconnections create inter-level electrical interconnections between said individual screen-printed conductors. The cathode plate is positioned over the connector ridge. The cathode plate has a plurality of die bond pads facing the faceplate rear surface and aligned with the upper-level conductors.

Abstract: A component having a movable micromechanical function element arranged in a cavity having a cover layer supported by webs or pillar-like supports is provided. The movable element is potentially covered with a termination layer for closing the etching holes present in the cover layer. Electrical terminals of the movable part, the cover layer and doped regions produced in the substrate as a cooperating electrode enable the realization of an acceleration sensor that is easy to mount in a housing.

Abstract: The top-side (n-type) electrode and bottom-side (p-type) electrode of a Si chip with a p-n junction are pressed against a Cu cathode electrode and a Cu anode electrode via Mo plates respectively, thereby establishing electrical connection. The inner wall of a case is round and the Si chip is almost square. The top of the case is covered with ceramic, for example. A washer is a compression member. A chip frame holds the Si chip and Mo plates in compression positions and simultaneously determines their locations within the case. Specifically, the side face of the Si chip is not flush with the side face of each of the Mo plates. This enables the chip frame to make the creepage distance longer. Since the chip frame is a single chip frame without any joint, the creepage distance between the anode and cathode electrodes is defined by part of the chip frame that faces part of the surface of the Si chip and parts of the surfaces of the Mo plates sandwiching the Si chip between them.

Abstract: Disclosed are an improved semiconductor memory cell suitable for high integration and a novel method of fabricating the same. The memory cell has a large capacitance and a small area. The memory cell also has a plurality of bit-lines buried in an isolation region in a semiconductor substrate. The bit-line has a very small width and thickness thereby reducing a parasitic capacity between the bit-line and the semiconductor substrate. The memory cell may further be provided with a noise shielding line. Further, disclosed is a novel memory cell array of a semiconductor memory. The buried bit-line is coupled with a bit-line connecting sub-arrays and both are separated by a insulation film. A plurality of pairs of the bit-lines are arranged in rows. A word-line is coupled with a sub-word line and both are separated by a insulation film. A plurality of pairs of the word-lines are arranged in columns. The memory cells are arranged at the intersections of the buried bit-lines and the word-lines.

Abstract: An independent active region K42 is composed by consecutively providing the source region S42 and S53 of the memory cell MC42 and MC53 between the word line WL2, WL3. The memory cell MC42 and MC53 are connected to the word line WL2, WL3 respectively. Another independent active region K53 is composed by consecutively providing the drain region D53 and D64 of the memory cell MC53 and MC64 between the word line WL3, WL4. The bit line BL3 is formed by connecting each of the independent active regions K30, K31, K32 and K33 with polysilicon respectively. Each of the independent active regions include each of the drain regions D41, D42, D43 and D44 of the memory cells MC41, MC42, MC43 and MC44. Also, the bit line BL4 is formed by connecting each of the independent active regions K41, K42, K43 and K44 with polysilicon respectively. Each of the independent active regions comprises the source regions S41, S42, S43 and S44 respectively.