Abstract: Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

Abstract: Semiconductor packages are disclosed. One semiconductor package includes a semiconductor die with an active surface, an opposite inactive surface, and four peripheral side surfaces. A substrate of the semiconductor package is coupled to one side surface of the semiconductor die. Bond pads of the active surface are coupled to a substrate first surface that is coplanar with the active surface. External interconnects, e.g., solder balls, are formed on a second substrate surface that is perpendicular to the active surface. An insulating layer, e.g., an encapsulant, together covers the active surface and the substrate first surface. An alternative semiconductor package includes two substrates, each attached to a respective one of two opposed side surfaces of the semiconductor die. The remaining two side surfaces of the semiconductor die are exposed. The external interconnects are formed on a third substrate surface that is coplanar with the inactive surface of the semiconductor die.

Abstract: A memory array layer for use in a 3D RRAM is formed, with peripheral circuitry, on a silicon substrate; layers of silicon oxide, bottom electrode material, silicon oxide, resistor material, silicon oxide, silicon nitride, silicon oxide, top electrode and covering oxide are deposited and formed. Multiple memory array layers may be formed on top of one another. The RRAM of the invention may be programmed in a single step or a two step programming process.

Abstract: In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has above the gate dielectric film a gate electrode film made of silicon germanium chosen as its main constituent material, or alternatively in a semiconductor device which has beneath the gate dielectric film a channel made of silicon as its main constituent material and which has below the channel a channel underlayer film made of silicon germanium as its main constituent material, a specifically chosen dopant, such as cobalt (Co) or carbon (C) or nitrogen (N), is added to the gate electrode and the channel underlayer film, for use as the unit for suppressing diffusion of germanium in the gate electrode or in the channel underlayer film.

Abstract: A thin film transistor for use in an active matrix liquid crystal display includes a substrate, a source and a drain regions, and at least a gate electrode. The substrate includes therein a plurality of intrinsic regions, at least one first doped region and two second doped regions. The first doped region is disposed between the plurality of intrinsic regions. The plurality of intrinsic regions are linked together to form a connection structure via the first doped region, and the two second doped regions are disposed at both ends of the connection structure, respectively. The source and the drain regions are coupled to the two second doped regions disposed at both ends of the connection structure, respectively. The gate electrode is disposed over the plurality of intrinsic regions, such that the periphery of each of the plurality of intrinsic regions and the periphery of a corresponding gate electrode are substantially aligned with each other.

Abstract: A system and method of processing a substrate including loading a substrate into a plasma chamber and setting a pressure of the plasma chamber to a pre-determined pressure set point. Several inner surfaces that define a plasma zone are heated to a processing temperature of greater than about 200 degrees C. A process gas is injected into the plasma zone to form a plasma and the substrate is processed.

Abstract: A semiconductor device includes an n-type semiconductor substrate (1) including a p-type collector layer (2) formed in a second main surface side thereof, a trench (13) is formed in a peripheral portion of the semiconductor substrate (1) so as to surround the inside and reach the collector layer (2) from a first main surface of the semiconductor substrate (1), and a p-type isolation region (14) formed by diffusion from a sidewall of the trench (13) is provided to be connected to the collector layer (2). The trench (13) is filled with a filling material (16).

Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

Abstract: A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, intergate dielectric layer, tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. The second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is between each of the first stacked gate structures, and between each of the second stacked gate structures and adjacent first stacked gate structure. The floating gate is between the control gate and substrate. The inter-gate dielectric layer is between the control and floating gates. The tunnel oxide is between the floating gate and substrate. The doping regions are under the first stacked gate structure, and the source/drain regions are in the exposed substrate.

Abstract: A semiconductor device with integrated circuits includes superimposed layers provided at different levels on a substrate, and including a metal strip (3) formed in a reference layer and through which an electric current passes, a metal ground plane (4) formed in a layer situated at a level lower than the reference layer and having a slit (5) which lies below the strip while running alongside it, an electrostatic shield (6) formed in a layer located at a level lower than the ground plane and comprising a multiplicity of spaced out bands (7), made of an electrically-conducting material, that extends across the slit, and conducting junctions (4a, 4b) making it possible to electrically connect the ends of each band to the parts of the ground plane situated on either side of its slit.

Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116?) and then annealing the substrate so as to cause the regions of the lower portion (140?) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).

Abstract: Disclosed is an LCD driver integrated circuit package and a chip on glass type LCD device using the package. The LCD driver integrated circuit package includes a mold that has signal output bumps and signal input bumps formed thereon, wherein the signal output bumps and the signal input bumps have different surface areas that contact the mold and an adjacent conductive film. Due to the different contact surface areas, different amounts of pressure are applied to different parts on the conductive film when a force is applied to the mold. One or more bump pressure control patterns are formed on the mold compensate for the difference in pressure caused by this difference between the total contact areas. Accordingly, the LCD driver integrated circuit package can be mounted on a chip on glass type LCD panel without causing device failure.

Abstract: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the creation of a new class of solide state chemical sensors. Detection of the following chemical species was established: hydrogen, deuterium, carbon monoxide, molecular oxygen. The detector (1b) consists of a Schottky diode between an Si layer and an ultrathin metal layer with zero force electrical contacts.

Abstract: A multiple layered wafer structure having, on a semiconductor substrate, a first dielectric layer, a single crystal semiconductor layer formed on the dielectric layer, a semiconductor nano-crystal layer formed on the single crystal semiconductor layer, and a second dielectric layer formed on the semiconductor nano-crystal layer. A laser is irradiated from the side of the second dielectric layer, to thereby separate the second dielectric layer from the others of the multiple layered wafer structure.

Abstract: The semiconductor device has a security coating with embedded magnetic particles and magnetoresistive sensors. This renders possible a measurement of the impedance of security elements defined by magnetoresistive sensors and security coating. If initial values of the impedance are stored, actual values can be compared therewith to see if the device has not been electrically probed or modified. Such a comparison can be used to check the authenticity of the device.

Abstract: The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.

Abstract: A resin sealing-type semiconductor device comprises a first semiconductor chip 15 with a large amount of heat generation, whose external electrode leading-out bonding pads 16 are wire-bonded to respective outer leads 25A and a second semiconductor chip 17 smaller in the amount of heat generation than the first semiconductor chip, whose external electrode leading-out bonding pads 18 are wire-bonded to respective outer leads 25A, wherein the first semiconductor chip 15 is molded by a high thermal conductive resin 28, and the second semiconductor chip 17 and the first semiconductor chip 15 molded by the high thermal conductive resin are integrally molded by a non-high thermal conductive resin 31. A method includes manufacturing the resin sealing-type semiconductor device.

Abstract: A semiconductor component having a memory cell coupled to a trench line and a method for manufacturing the semiconductor component. Trenches having sidewalls are formed in a semiconductor substrate and a trench line is formed in each trench. A polysilicon insert is formed between the trench line and each sidewall of the trench. A column of memory cells is formed between the trenches where each memory cell of the column of memory cells has a gate structure, a source region, and a drain region. The source regions of the column of memory cells are electrically coupled to the trench line on one side of the column of memory cells via one of the polysilicon inserts. The drain regions of the column of memory cells are electrically coupled to the trench line adjacent the opposite side of the column of memory cells via another of the polysilicon inserts.

Abstract: A memory device using vertical nanotubes includes an array of first electrodes arranged in strips in a first direction, a dielectric layer deposited on the array of first electrodes, the dielectric layer having a plurality of holes arranged therein, an array of nanotubes for emitting electrons, the array of nanotubes contacting the array of first electrodes and vertically growing through the plurality of holes in the dielectric layer, an array of second electrodes arranged in strips in a second direction on the dielectric layer, the array of second electrodes contacting the array of nanotubes, wherein the second direction is perpendicular to the first direction, a memory cell positioned on the array of second electrodes for trapping electrons emitted from the array of nanotubes, and a gate electrode deposited on an upper surface of the memory cell for forming an electric field around the array of nanotubes.

Abstract: The circuit element has a first layer composed of an electrically insulating substrate material and a first electrically conductive material which is in the form of at least one discrete area such that it is embedded in the substrate material and/or is applied to the substrate material. Furthermore, it has a second layer having a second electrically conductive material, and a monomolecular layer composed of redox-active bispyridinium molecules, which is arranged between the first layer and the second layer. The bispyridinium molecules are immobilized on the electrically conductive material which is in the form of at least one discrete area, and make electrical contact with the second electrical material of the second layer. Furthermore, electrically inert molecules are immobilized on the first layer, which molecules form a matrix which surrounds the at least one discrete area with the monomolecular layer composed of bispyridinium molecules.