Patents Examined by Mai-Huong Tran
  • Patent number: 6998713
    Abstract: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: February 14, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Yasumori Narizuka, Mitsuko Itou, Yoshihide Yamaguchi, Hiroyuki Tenmei
  • Patent number: 6995411
    Abstract: An image sensor has a vertically integrated thin-film photodiode.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: February 7, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Dun-Nian Yaung, Sou-Kuo Wu, Ho-Ching Chien
  • Patent number: 6992342
    Abstract: A magnetic memory device, in which a tunnel magneto resistance element that establishes a connection between a write word line (first interconnection) and a bit line (second interconnection) is provided within a region in which the write word line and the bit line cross in a grade-separated manner. The magnetic memory device comprises a through hole that is provided in such a manner that is insulated from the write word line and also extending through the write word line so as to establish a connection between the tunnel magneto resistance element and a second landing pad (interconnection layer) lower than the write word line, and a contact that is formed in the through hole through a side wall barrier film so as to establish a connection between the tunnel magneto resistance element and the second landing pad.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: January 31, 2006
    Assignee: Sony Corporation
    Inventors: Makoto Motoyoshi, Minoru Ikarashi
  • Patent number: 6992381
    Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: January 31, 2006
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, James G. Maveety, Alan M. Myers, Quat T. Vu, Ravi Prasher, Ravi Mahajan, Gilroy Vandentop
  • Patent number: 6992330
    Abstract: Image display panel of the “top-emitting” OLED type having, on the internal face of the front plate, which plate faces the observer, an array of cavities or grooves that are distributed between the light-emitting cells and contain an absorbent agent intended to absorb, in particular, traces of oxygen and/or water vapor liable to degrade the organic electroluminescent cells. The lifetime of the panels is thereby improved.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: January 31, 2006
    Assignee: Thomson Licensing
    Inventors: Christophe Fery, Gunther Haas
  • Patent number: 6992348
    Abstract: Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: January 31, 2006
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kleint, Joachim Deppe, Christoph Ludwig, Jens-Uwe Sachse
  • Patent number: 6989564
    Abstract: A NOR type semiconductor storage comprising memory cells, word lines, local and main source lines of metal and bit lines is disclosed. Two adjacent cells on a column form one set and share the drain region. Two adjacent cell sets on a column share the source region. Cell columns are isolated by trench type element isolation regions. A local source line run on and is connected to the source regions of the cells on a row. The main source lines are arranged intermittently between the bit line columns and are connected to the local source lines. A height of embedded layers in the element isolation regions under the local source lines or a height of a portion of the embedded layers contacting the substrate is lower than an upper surface of the source regions under the local source lines. The local source lines are connected to the well region.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: January 24, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eiji Sakagami
  • Patent number: 6984847
    Abstract: An organic electroluminescent device includes first and second substrates facing and spaced apart from each other; a gate line on an inner surface of the first substrate; a semiconductor layer over the gate line, the semiconductor layer overlying a surface of the first substrate; a data line crossing the gate line; a data ohmic contact layer under the data line, the data ohmic contact layer having the same shape as the data line; a power line parallel to, or substantially parallel to, and spaced apart from the data line, the power line including the same material as the gate line; a switching thin film transistor connected to the gate line and the data line, the switching thin film transistor using the semiconductor layer as a switching active layer; a driving thin film transistor connected to the switching thin film transistor and the power line, the driving thin film transistor using the semiconductor layer as a driving active layer; a connection pattern connected to the driving thin film transistor, the co
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: January 10, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Jae-Yong Park, Kwang-Jo Hwang
  • Patent number: 6984862
    Abstract: A storage device includes a first semiconducting layer having a p-dopant and a second semiconducting layer having an n-dopant, disposed on the first semiconducting layer forming a junction between the first and the second semiconducting layers. The storage device also includes a charge trapping structure disposed on the second semiconducting layer and a conductive gate, wherein the conductive gate and the charge trapping structure move relative to the other, wherein an electric field applied across the second semiconducting layer and the conductive gate traps charge in the charge trapping structure.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: January 10, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hang Liao, Zhizhang Chen, Alexander Govyadinov, Leslie Louis Szepesi, Jr., Heon Lee
  • Patent number: 6984877
    Abstract: A semiconductor package such as a bumped chip carrier (BCC) package has projections extending from a lower surface of a resin encapsulant. Each projection has a concave depression formed thereon. By reflowing a solder layer, external terminals are formed to cover the projections. An interface between the terminals and the projections increases in area, relative to conventional structures, because of the concave depressions. Therefore, the adhesive strength between the terminals and the projections also increases, and, when the BCC package is mounted on a next-level circuit board through the terminals, solder joint is also improved in reliability.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: January 10, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Suk Lee, Cheul-Joong Youn
  • Patent number: 6982471
    Abstract: The present invention relates to a semiconductor memory device including a fuse box wherein the layout of a fuse box used to control a memory cell array is improved, a fuse box is divided into a plurality of blocks, and an index mark is applied to every fuse box or to every block so that a user may recognize each fuse box. In an embodiment, there is provided a semiconductor memory device including a fuse box comprising a plurality of cell matrices and a fuse box. The plurality of cell matrices are arranged adjacently each other. The fuse box is defined by a fuse barrier layer formed at a side of the plurality of cell matrices, wherein the fuse box comprises a plurality of cell matrices, wherein the fuse box comprises a plurality of fuses shared by the plurality of cell matrices, and the fuse barrier layer is configured to have a length long enough to be shared by the plurality of cell matrices.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: January 3, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kang Seol Lee, Ji Hoon Lee
  • Patent number: 6982194
    Abstract: A semiconductor device, comprises a first electrode, a semiconductor film, a first insulating film and a second insulating film formed between the semiconductor film and the first electrode, a second electrode, and a third insulating film formed between the semiconductor film and the second electrode. The semiconductor film is formed on a flat surface of the second insulating film. A cross portion where the first electrode and the second electrode cross the semiconductor film at the same position is formed. The first electrode and the second electrode are connected to each other through an opening made in the first insulating film and the second insulating film outside the cross portion.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: January 3, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akira Tsunoda, Shunpei Yamazaki, Jun Koyama
  • Patent number: 6979896
    Abstract: An electrical device includes electrical contact pads, a supply voltage bus and an interconnection circuit. The electrical contact pads receive a supply voltage, and the bus is electrically connected to the electrical contact pads. For each electrical contact pad, the interconnection circuit forms a redundant connection between the bus and the electrical contact pad. The electrical device may include a passivation layer that includes windows to establish electrical contact between the electrical contact pads and the supply voltage bus. This window may be elongated in a path that is generally aligned with the path along which the supply voltage bus extends.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: December 27, 2005
    Assignee: Intel Corporation
    Inventor: Krishna Seshan
  • Patent number: 6977428
    Abstract: What is invented is a semiconductor device (10) comprising a pellet (12) having a ground electrode (18), an outside signal terminal (15) connected to the pellet (12), so as to receive signal which is likely to include noise. Therein, said outside signal terminal (15) is surrounded with a ground terminal (17) connected to said ground electrode (18) in at least a half periphery.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: December 20, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura
  • Patent number: 6977405
    Abstract: In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: December 20, 2005
    Assignee: Infineon Technologies, AG
    Inventors: Jörn Lützen, Bernd Goebel, Dirk Schumann, Martin Gutsche, Harald Seidl, Martin Popp, Alfred Kersch, Werner Steinhögl
  • Patent number: 6977424
    Abstract: An electrically pumped optical device includes a semiconductor active region and a backward diode. Both of these structures are located in the current path of the optical device, which is oriented primarily vertically. The active region has a finite extent along at least one lateral dimension. The overall structure improves the electrical performance of the device.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: December 20, 2005
    Assignee: Finisar Corporation
    Inventors: Jeffrey D. Walker, Daniel A. Francis, Peter W. Evans, Paul Liu
  • Patent number: 6977410
    Abstract: Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: December 20, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Giovanni Naso, Elio D'Ambrosio
  • Patent number: 6974975
    Abstract: A solid-state imaging device comprising: a semiconductor substrate having a first surface; and a plurality of light-receiving sections arranged in an array pattern on the first surface of the semiconductor substrate, the solid-state imaging device reading a stored electric charge in each of the light-receiving sections, wherein each of the light-receiving sections comprises: a first signal electric charge storage section that stores a first signal electric charge corresponding to an incident light energy; and a second signal electric charge storage section that stores at least part of an excessive electric charge, the at least part of the excessive electric charge being captured from the first signal electric charge storage section, when the electric charge stored in the first signal electric charge storage section exceeds a saturated electric charge amount of the first signal electric charge section to form the excessive electric charge.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: December 13, 2005
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Makoto Shizukuishi
  • Patent number: 6974984
    Abstract: Methods of depositing various metal layers adjacent to a ferroelectric polymer layer are disclosed. In one embodiment, a collimator may be used during a sputtering process to filter out charged particles from the material that may be deposited as a metal layer. In various embodiments, a metal layer may contain at least one of an intermetallic layer, an amorphous intermetallic layer, and an amorphized intermetallic layer.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Hitesh Windlass, Ebrahim Andideh, Daniel C. Diana, Mark Richards, William C. Hicks
  • Patent number: 6975002
    Abstract: An SOI single crystalline chip structure includes an active device layer for having at least one SOI device placed thereon, a buried oxide layer under the active device layer, a metal layer under the buried oxide layer, and a silicon substrate under the metal layer. At least one through hole passing through the buried oxide layer is disposed at a first predetermined position of the buried oxide layer, and at least one concave hole not passing through the buried oxide layer is disposed at a second predetermined position of the bottom surface of the buried oxide layer.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: December 13, 2005
    Assignee: Via Technologies, INC
    Inventors: Ray Chien, Honda Huang