Abstract: The invention generally relates to the use of poly-3,3?-dialkyl-2,2?:5?,2?-terthiophenes as charge transport materials or semiconductors in electrooptical, electronic or electroluminescent devices, and to charge transport and semiconducting components and devices comprising poly-3,3?-dialkyl-2,2?:5?,2?-terthiophenes.

Abstract: A film carrier tape for mounting electronic devices thereon having a mounting unit in which a wiring pattern is formed by etching on a base material, wherein the mounting unit has a target mark to be a reference of an alignment for carrying out final defect marking in a target position on the mounting unit by marking means as a pattern formed on the base material by the etching, and a defect marking method using the same are provided.

Abstract: A method of manufacturing a plurality of semiconductor chip packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A first microelectronic element is arranged with the substrate and contacts on the microelectronic element are connected to the substrate. A conductive member is placed on top of the first microelectronic element and is used to support a second microelectronic element. The second microelectronic element is arranged with the conductive member in a top and bottom position. The second microelectronic element is then also connected by leads from contacts on the second microelectronic element to pads and terminals on the circuitized substrate. The conductive member is then connected to a third pad or set of pads on the substrate. An encapsulant material may be deposited so as to encapsulate the leads and at least one surface of the microelectronic elements.

Abstract: The present invention is a metal bond pad that provides electrical and mechanical connection to an integrated circuit (IC). The metal bond pad is configured to accommodate for probe travel during probing measurements, without modifying the size of the passivation opening of the bond pad. This enables higher density of active devices on the IC and therefore increases integration and lowers IC cost. The metal bond pad for the integrated circuit includes a substrate, a first metal layer, and a second metal layer. The substrate has the first metal layer disposed therein, having an opening from the top surface of the substrate. The second metal layer has a first-end portion, a second-end portion and a center portion disposed between the first-end portion and the second-end portion. The center portion of the second metal layer is aligned with the opening in the substrate and a bottom surface of the center portion is in contact with the top surface of the first metal layer.

Abstract: An insulated gate transistor is comprised of a semiconductor thin film, a first gate insulating film formed on a main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film. The insulated gate transistor is controlled by injecting carriers of the second conductivity type into the semiconductor thin film from the third semiconductor region, and thereafter applying a first electric potential to the first conductive gate to form a channel of the first conductivity type on a portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region.

Abstract: There are provided a first reference layer, in which a direction of magnetization is fixed, and a storage layer including a main body, in which a length in an easy magnetization axis direction is longer than a length in a hard magnetization axis direction, and a projecting portion provided to a central portion of the main body in the hard magnetization axis direction, a direction of magnetization of the storage layer being changeable in accordance with an external magnetic field.

Abstract: A register setting method which facilitates writing of change information into a register for storing operation condition information that defines the operation of a device. The method includes the steps of storing first operation condition information in a first register, storing second operation condition information in a second register, changing the first operation condition information, and when the first operation condition information is changed, changing the second operation condition information to changed first operation condition information in accordance with change information for changing the first operation condition information.

Abstract: A magnetic tunnel junction (MTJ), which is useful in magnetoresistive random access memories (MRAMs), has a free layer which is a synthetic antiferromagnet (SAF) structure. This SAF is composed of two ferromagnetic layers that are separated by a coupling layer. The coupling layer has a base material that is non-magnetic and also other materials that improve thermal endurance, control of the coupling strength of the SAF, and magnetoresistance ratio (MR). The preferred base material is ruthenium and the preferred other material is tantalum. Furthering these benefits, cobalt-iron is added at the interface between the tantalum and one of the ferromagnetic layers. Also the coupling layer can have even more layers and the materials used can vary. Also the coupling layer itself can be an alloy.

Abstract: A display device capable of switching over between vertical and horizontal display on a screen without using a frame memory is provided. A display device has a source signal line driver circuit (102), a first gate signal line driver circuit (103), and a second gate signal line driver circuit (104). The scanning direction of the first gate signal line driver circuit (103) is perpendicular to the scanning direction of the source signal line driver circuit (102), and the scanning direction of the second gate signal line driver circuit (104) is perpendicular to the scanning direction of the first gate signal line driver circuit (103). During normal display, vertical scanning of the screen is performed by the first gate signal line driver circuit (103). Images are displayed in a direction that is in accordance with the scanning direction of the first gate signal line driver circuit (103).

Abstract: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: A light-emitting semiconductor device comprises a III-Nitride active region and a III-Nitride layer formed proximate to the active region and having a thickness that exceeds a critical thickness for relaxation of strain in the III-Nitride layer. The III-Nitride layer may be a carrier confinement layer, for example. In another aspect of the invention, a light-emitting semiconductor device comprises a III-Nitride light emitting layer, an InxAlyGa1-x-yN (0?x?1, 0?y?1, x+y?1), and a spacer layer interposing the light emitting layer and the InxAlyGa1-x-yN layer. The spacer layer may advantageously space the InxAlyGa1-x-yN layer and any contaminants therein apart from the light emitting layer. The composition of the III-Nitride layer may be advantageously selected to determine a strength of an electric field in the III-Nitride layer and thereby increase the efficiency with which the device emits light.

Abstract: A magnetic tunneling junction (MTJ) memory cell for a magnetic random access memory (MRAM) array is formed as a chain of magnetostatically coupled segments. The segments can be circular, elliptical, lozenge shaped or shaped in other geometrical forms. Unlike the isolated cells of typical MTJ designs which exhibit curling of the magnetization at the cell ends and uncompensated pole structures, the present multi-segmented design, with the segments being magnetostatically coupled, undergoes magnetization switching at controlled nucleation sites by the fanning mode. As a result, the multi-segmented cells of the present invention are not subject to variations in switching fields due to shape irregularities and structural defects.

Abstract: When a p-type MgxZn1-xO-type layer is grown based on a metal organic vapor-phase epitaxy process, the p-type MgxZn1-xO-type layer is annealed in an oxygen-containing atmosphere during and/or after completion of the growth of the p-type MgxZn1-xO-type layer. In addition, a vapor-phase epitaxy process of a semiconductor layer is proceed while irradiating ultraviolet light to the surface of a substrate to be grown and source gasses. In addition, when a MgxZn1-xO-type buffer layer that is oriented so as to align the c-axis thereof to a thickness-wise direction is formed by an atomic layer epitaxy process, a metal monoatomic layer is grown at first. In addition, a ZnO-base semiconductor active layer is formed by using a semiconductor material mainly composed of ZnO containing Se or Te. A light emitting device is formed by using these techniques.

Abstract: A micromechanical switch comprises a substrate, at least one pair of support members fixed to the substrate, at least one pair of beam members placed in proximity and parallel to each other above the substrate, and connected to one of the support members, respectively, each of the beam members having a moving portion which is movable with a gap with respect to the substrate, and a contact portion provided on the moving portion, and a driving electrode placed on the substrate between the pair of beam members to attract the moving portions of the beam members in a direction parallel to the substrate with electrostatic force so that the contact portions of the beam members which are opposed to each other are short-circuited.

Abstract: A semiconductor laser module has a stem base and a stem block provided thereon. A submount is fixed on the block, and a laser diode (LD) is mounted on the submount. Transmission lines are formed on the submount and connected to the anode and cathode of the LD. Lead pins extend through the stem base to be connected to the transmission lines. A photodetector is disposed, below the LD, on the stem base. Aperture for placement of the photodetector is formed in the submount, and the photodetector is placed at least partially in this aperture.

Abstract: In a matrix-shaped configuration of memory transistors, word lines are disposed on a top side of a semiconductor body and are parallel to one another. Bit lines run transversely with respect thereto and are formed by polysilicon strips which are applied on the top side and are isolated from the semiconductor body by barrier layers functioning as diffusion barriers.

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a Metal-Insulator-Metal (MIM) capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the MIM capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.

Abstract: A visible light transmitting structure with photovoltaic effect comprises a transparent substrate and a PN junction layer having a P type semiconductor and an N type semiconductor, which is formed on the substrate. The visible light transmitting structure with photovoltaic effect may be used as a windowpane of a house or a business place for shutting out harmful ultraviolet rays by passing visible light through the windowpane.

Abstract: A semiconductor memory device includes a memory cell, and first and second capacitive elements. The memory cell has a pair of inverters each including first and second driver nMOS transistors and first and second TFTs, and first and second access nMQS transistors. The first and second capacitive elements is connected to the drain of first and second access nMOS transistors, the drain of first and second driver nMOS transistors, and the drain of first and second TFTs. The gate width of first and second driver nMOS transistors is set at most 1.2 times longer than the gate width of first and second access nMOS transistors.