Abstract: In a semiconductor device having a trench-gate structure in which polysilicon doped with boron is embedded in a trench, insulating film formed on the inner wall of the trench comprises ONO film, and silicon nitride film constituting the ONO film is formed to such film thickness and film quality that boron can be suppressed from passing through the silicon nitride film. Silicon oxide film is formed so that a top oxide film is thin and a bottom oxide film is thick.

Abstract: A semiconductor multi-package module having stacked first and second packages, each package including a die attached to a substrate, in which the first and second substrates are interconnected by wire bonding, and wherein at least one said package comprises a stacked die package. Also, a method for making a semiconductor multi-package module, by providing a stacked die molded first package including a first package substrate, affixing a second molded package including a second substrate onto an upper surface of the first package, and forming z-interconnects between the first and second substrates.

Abstract: Disclosed in a method of planarizing a silicon on insulator (SOI) structure. The invention performs a first chemical mechanical planarization (CMP) process on an insulator (e.g., oxide) layer. However, this first CMP process creates scratches on the insulator layer. The invention forms a polish stop insulator (e.g., nitride) over the insulator layer in, for example, a liquid phase chemical vapor deposition (LPCVD) process. The polish stop insulator fills in the scratches. The invention then forms an opening through the insulator layer and through the polish stop insulator (e.g., in a reactive ion etching (RIE) process) and deposits a conductor within the opening. The invention performs a second CMP process on the conductor. The polish stop insulator is harder than the insulating layer and prevents the second CMP process from scratching the insulator layer. The invention removes portions of the polish stop insulator to leave the polish stop insulator only within the scratches.

Abstract: The present invention discloses a laminated chip electronic device and a method of manufacturing the same. In the laminated chip electronic device and the method of manufacturing the same according to the present invention, a body is made of a non-linear resistance coefficient material and has a plurality of conductive layers formed therein; an insulating layer is formed on the top, bottom, front and back surfaces of the body; and two electrodes are formed at the two ends of the body and electrically connected to the terminals of the conductive layers, respectively. Furthermore, in the present invention, two soldered interface layers are formed on the two electrodes, respectively.

Abstract: A method for processing a semiconductor substrate includes providing a substrate having at least one filter region with a plurality of bond pads in it. Metal is deposited above the bond pads, to reduce the bond pad step height. A planarization layer is formed such that the deposited metal has a height near to a height of the planarization layer. At least one color resist layer is formed above the planarization layer.

Abstract: A hybrid integrated circuit (IC) package substrate at least comprising a plurality of patterned conductive layers stacked over each other. The outermost patterned conductive layer has a plurality of bonding pads thereon. The hybrid IC package substrate also has a plurality of dielectric layers respectively sandwiched between two neighboring patterned conductive layers. At least one of the dielectric layers is a ceramic dielectric layer and at least one of the remaining dielectric layers is an organic dielectric layer. There is also a plurality of vias passing through at least one of the dielectric layers for connecting at least two patterned conductive layers electrically.

Abstract: The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip, through the core to the bottom surface where signals exit the carrier to the printed wiring board. This fanning out is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip thereby increasing the density of circuits escaping the footprint area.

Abstract: A magnetic memory device includes a magnetoresistance configured to store information. A first wiring is provided along a first direction. The first wiring has a function of applying a magnetic field to the magnetoresistance element. The first wiring has a first surface and a second surface. The second surface faces the magnetoresistance element and the first surface is opposite to it. The second surface is smaller in width than the first surface.

Abstract: It is ideal to amplify voltage within a pixel to obtain sufficient sensitivity and low noise characteristics in a short storing time in order to acquire high-speed images, but no method has existed to satisfy the three requirements of the electronic shutter operation, removal of reset noise and signal voltage amplification. To solve this problem, the present invention takes the ratio of the capacitor C1 at point V1 and capacitor C2 at point V2 to be large, and transfers charges from V1 to V2, thereby enabling the signal voltage to be amplified. Moreover, the reset noise component sampled and included in VFD0 before opening TX is the same amount as the reset noise included in the voltage after TX is opened and the ?VFD of change occurred, so the reset noise is removed by taking out the amount of change ?VFD and amplifying the signal voltage. By returning R to 3V, the charge injection from the section V1 does not occur, thereby the voltage of V2 is held as is, and enters into storage status.

Abstract: An organic memory cell made of two electrodes with a selectively conductive media between the two electrodes is disclosed. The selectively conductive media contains an organic layer and passive layer. The selectively conductive media is programmed by applying bias voltages that program a desired impedance state for a memory cell. The desired impedance state represents one or more bits of information and the memory cell does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media is read by applying a current and reading the impedance of the media in order to determine the impedance state of the memory cell. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.

Abstract: There are included the steps of preparing a wiring substrate having a wiring pattern on a surface, bonding a connection terminal of electronic chip, which has a predetermined element and the connection terminal on one surface, to the wiring pattern of the wiring substrate by a flip-chip bonding, forming an insulating film on the wiring substrate to have a film thickness that covers the electronic chip, or a film thickness that exposes at least another surface of the electronic chip, and reducing a thickness of the electronic chip by grinding another surface of the electronic chip and the insulating film.

Abstract: To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric protective layer (5) and a dielectric auxiliary layer (16) are deposited on a first electrode (2). The protective layer and the auxiliary layer (16) are then opened up (17) via the first electrode. Then, a dielectric layer (6) is produced, and the metal track stack (7, 8, 9) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.

Abstract: A memory cell for use in a magnetic random access memory (MRAM) circuit includes at least first and second transistors formed in a semiconductor layer. A first insulating layer is formed on at least a portion of the first and second transistors. The memory cell further includes a first magnetic storage element formed on at least a portion of the first insulating layer, at least a second insulating layer formed on at least a portion of the first magnetic storage element, and at least a second magnetic storage element formed on at least a portion of the second insulating layer. The first and second magnetic storage elements are electrically connected to the first and second transistors, respectively.

Abstract: Semiconductor equipment includes a semiconductor substrate, a plurality of first type semiconductor devices having first and second device regions, a plurality of second type semiconductor devices having the first and second device regions, and upper and lower layer wirings disposed on the substrate. The upper and lower layer wirings electrically connect a plurality of first and second device regions together with a parallel connection, respectively. The lower layer wiring includes a first contact for connecting to the first device region and a second contact for connecting to the second device region. The first contact is concentrated into a predetermined area. The second contact surrounds the first contact. The upper layer wiring disposed on the predetermined area provides a pad area for connecting to an external circuit.

Abstract: The present invention provides hybrid microelectronic memory device, comprising: (a) a substrate having a surface, a first region of first work function adjacent the surface, and a second region of second work function adjacent the surface and adjacent the first region; (b) a film comprising redox-active molecules on the first and second regions; and (c) an electrode connected to the film. The present invention further provides a hybrid microelectronic memory device, comprising: (a) a substrate having surface and a structure or region such as a diode for increasing the retention time of the device formed adjacent the surface; (b) a film comprising redox-active molecules on or associated with the region or structure; and (c) an electrode connected to the redox active molecules opposite the substrate surface. Methods of using such devices are also described.

Abstract: Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode and having an L-shaped/reversed L-shaped cross-sectional shape, and a semiconductor layer extending over the gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode.

Abstract: A semiconductor modulator is disclosed which exhibits a negative alpha parameter at low operating bias. The device includes at least two barrier layers with a quantum well layer therebetween. An additional layer is formed adjacent to the quantum well layer, the additional layer having a bulk bandgap energy greater than the quantum well layer so as to form a stepped well between the barrier layers.

Abstract: In plating on an Si substrate, it has been strongly demanded to apply a treatment for providing an excellent adhesion so as to resist a post-processing such as polishing and for facilitating plating. Then, provided is a plated substrate adapted for hard disk medium comprising an Si single crystal; an amorphous layer on the substrate, the amorphous layer having thickness of 2 to 200 nm and containing Si and one or more metals selected from a group consisting of Ni, Cu and Ag; a multicrystal layer on the amorphous layer, the multicrystal layer having thickness of 5 to 1000 nm and containing Si and one or more metals selected from a group consisting of Ni, Cu and Ag.

Abstract: A method of fabricating a trench capacitor of a memory cell, includes providing a semiconductor substrate with a surface covered by a pad layer, forming a trench in the substrate, forming a first layer on the pad layer and on the surface of the trench, removing a portion of the first layer to form a residual first insulating layer, forming a first conductive layer on the residual first layer, removing a portion of the first conductive layer, removing a portion of the residual first layer, driving out charged elements from the first layer into the semiconductor substrate, to form a first doped substrate region, removing the first layer, forming a node nitride on the trench, forming a second conductive layer on the pad layer and on the trench, removing a portion of the second conductive layer to form a second doped substrate region in the trench.

Abstract: Micromachine systems are provided. An embodiment of such a micromachine system includes a substrate that defines a trench. First and second microelectromechanical devices are arranged at least partially within the trench. Each of the microelectromechanical devices incorporates a first portion that is configured to move relative to the substrate. Methods also are provided.