Abstract: A method of manufacturing an electronic device that comprises a microelectromechanical (MEMS) element, the method comprising the steps of: providing a material layer (34) on a first side of a substrate (32); providing a trench (40) in the material later (34); etching material from the trench (40) such as to also etch the substrate (32) from the first side of the substrate (32); grinding the substrate (32) from a second side of the substrate to expose the trench (40); and using the exposed trench (40) as an etch hole. The exposed trench (40) is used as an etch hole for releasing a portion of the material layer (34), for example a beam resonator (12), from the substrate (32). An input electrode (6), an output electrode (8), and a top electrode (10) are provided.

Abstract: (A) solid polymer particles being finely dispersed in the aqueous phase and containing pendant functional groups (a1) capable of strongly interacting and forming strong complexes with the metal of the surfaces to be polished, and pendant functional groups (a2) capable of interacting less strongly with the metal of the surfaces to be polished than the functional groups (a1); and (B) an organic non-polymeric compound dissolved in the aqueous phase and capable of interacting and forming strong, water-soluble complexes with the metal of the surfaces to be polished and causing an increase of the material removal rate MRR and the static etch rate SER of the metal surfaces to be polished with increasing concentration of the compound (B); a CMP process comprising selecting (A) and (B) and the use of the CMP agent and process for polishing wafers with ICs.

Abstract: The present invention relates to a plasma etching method with which a wide-gap semiconductor substrate can be etched with high accuracy. An inert gas is supplied into a processing chamber and plasma is generated from the inert gas, a bias potential is applied to a platen on which a wide-gap semiconductor substrate is placed, thereby making ions generated by the generation of plasma from the inert gas incident on the semiconductor substrate on the platen to thereby heat the semiconductor substrate. After the temperature of the semiconductor substrate reaches an etching temperature between 200° C. and 400° C., an etching gas is supplied into the processing chamber and plasma is generated from the etching gas and a bias potential is applied to the platen, thereby etching the semiconductor substrate while maintaining the temperature of the semiconductor substrate at the etching temperature.

Abstract: Described is a method for improving the flatness of a layer deposited on a doped polycrystalline layer, which includes reducing the grain size of the polycrystalline layer to decrease the out-diffusion amount of the dopant from the polycrystalline layer, and/or reducing the amount of the out-diffusing dopant on the surface of the polycrystalline layer.

Abstract: A method for manufacturing a printed circuit board enables a metal residue between wirings to be removed inexpensively without side etching of a copper layer while having sufficient insulation reliability for micro wiring working. The method includes forming a base metal layer directly at least on one face of an insulator film without an adhesive, and a copper coat layer formed on the base metal layer to form adhesiveless copper clad laminates, then forming a pattern on the adhesiveless copper clad laminates by an etching method. The etching method includes a process of etching treatment for the adhesiveless copper clad laminates with an iron (III) chloride solution or a copper (II) chloride solution containing hydrochloric acid and then, a process of treatment with an acid oxidant containing potassium permanganate.

Abstract: High quantum yield InP nanocrystals are used in the bio-technology, bio-medical, and photovoltaic, specifically IV, III-V and III-VI nanocrystal technological applications. InP nanocrystals typically require post-generation HF treatment. Combining microwave methodologies with the presence of a fluorinated ionic liquid allows Fluorine ion etching without the hazards accompanying HF. Growing the InP nanocrystals in the presence of the ionic liquid allows in-situ etching to be achieved. The optimization of the PL QY is achieved by balancing growth and etching rates in the reaction.

Abstract: A method of manufacturing a magnetic recording medium, includes, in the order recited, the steps of forming a mask protective film composed of carbon on a magnetic layer; forming a resist with a predetermined pattern on the mask protective film; forming a protective mask by etching the mask protective film using the resist as a mask; forming protrusions and recesses on a magnetic layer by etching the magnetic layer using the resist and the protective mask as masks; removing the protective mask, including removing the mask protective film comprised of carbon, using ultraviolet light with a principal wavelength not longer than 340 nm; and forming a protective layer on the magnetic layer having the protrusions and recesses formed thereon.

Abstract: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, wherein the adjuvant comprises a polyelectrolyte salt containing: (a) a mixture of a linear polyelectrolyte having a weight average molecular weight of 2,000˜50,000 with a graft type polyelectrolyte that has a weight average molecular weight of 1,000˜20,000 and comprises a backbone and a side chain; and (b) a basic material. CMP (chemical mechanical polishing) slurry comprising the above adjuvant and abrasive particles is also disclosed. The adjuvant comprising a mixture of a linear polyelectrolyte with a graft type polyelectrolyte makes it possible to increase polishing selectivity as compared to CMP slurry using the linear polyelectrolyte alone, and to obtain a desired range of polishing selectivity by controlling the ratio of the linear polyelectrolyte to the graft type polyelectrolyte.

Abstract: This disclosure relates to an etching composition containing at least one sulfonic acid, at least one compound containing a halide anion, the halide being chloride or bromide, at least one compound containing a nitrate or nitrosyl ion, and water. The at least one sulfonic acid can be from about 25% by weight to about 95% by weight of the composition. The halide anion can be chloride or bromide, and can be from about 0.01% by weight to about 0.5% by weight of the composition. The nitrate or nitrosyl ion can be from about 0.1% by weight to about 20% by weight of the composition. The water can be at least about 3% by weight of the composition.

Abstract: Disclosed are: a resin composition for pattern formation, which enables the stable formation of a pattern at a level of the wavelength of light; a method for forming a pattern having a sea-island structure using the composition; and a process for producing a light-emitting element that can achieve high luminous efficiency properties.

Abstract: A method for inspecting semiconductor wafers patterned by a photomask includes loading a first wafer and scanning a first image of the first wafer, loading a second wafer and scanning a second image of the second wafer, comparing the first and second images, and classifying a difference detected between the first and second images as a potential defect on the photomask. The potential defect includes a haze defect on the photomask.

Abstract: A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.

Abstract: The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.

Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.

Abstract: The present invention provides a dry etching method capable of readily providing rounded top edge portions, called top rounds, at trenches and vias formed by removal of a dummy material. The method of the present invention is a dry etching method for forming trenches or vias by removing a dummy material with its periphery surrounded by an interlayer oxide film, which method includes the steps of etching the dummy material to a predetermined depth, performing isotropic etching after the dummy material etching, and removing remaining part of the dummy material after the isotropic etching.

Abstract: A method for etching features into a silicon substrate disposed below a mask in a plasma processing chamber is provided. The silicon substrate is etched through the mask comprising a plurality of cycles, wherein each cycle comprises a sidewall deposition phase and an etch phase. The sidewall deposition phase comprises providing a flow of sidewall inorganic deposition phase gas comprising a silicon containing compound gas and at least one of oxygen, nitrogen or NOx, into the plasma processing chamber, forming a plasma from the sidewall deposition phase gas in the plasma processing chamber, and stopping the flow of the sidewall deposition gas into the plasma processing chamber. The etch phase comprises, providing a flow of an etching gas comprising a halogen component, forming a plasma from the etching gas in the plasma processing chamber, and stopping the flow of the etching gas.

Abstract: According to one embodiment, a semiconductor device manufacturing method is disclosed. The method can include polishing a film on a semiconductor substrate by pressing the film against a polishing pad. Polishing the film comprises performing first polishing in which an entrance temperature of the polishing pad is adjusted to 40° C. (inclusive) to 50° C. (inclusive), and an exit temperature of the polishing pad is adjusted to be higher by 5° C. or more than the entrance temperature. Polishing the film comprises performing second polishing in which the entrance temperature is adjusted to 30° C. or less, and the exit temperature is adjusted to be higher by 5° C. or more than the entrance temperature.

Abstract: A plasma processing method includes: etching an anti reflection coating film with plasma generated from an etching gas by using a resist film that is patterned as a mask, in a deposited film in which an Si-ARC film constituting the anti reflection coating film is formed on a layer to be etched and the ArF resist film is formed on the anti reflection coating film; and modifying the ArF resist film with plasma generated from a modifying gas including a CF4 gas, a COS gas and an Ar gas by introducing the modifying gas into a plasma processing apparatus, wherein the modifying is performed before the etching.

Abstract: A substrate processing method uses a substrate processing apparatus including a chamber for accommodating a substrate, a lower electrode to mount the substrate, a first RF power applying unit for applying an RF power for plasma generation into the chamber, and a second RF power applying unit for applying an RF power for bias to the lower electrode. The RF power for plasma generation is controlled to be intermittently changed by changing an output of the first RF power applying unit at a predetermined timing. If no plasma state or an afterglow state exists in the chamber by a control of the first RF power applying unit, an output of the second RF power applying unit is controlled to be in an OFF state or decreased below an output of the second RF power applying unit when the output of the first RF power applying unit is a set output.

Abstract: A method using an associated composition for chemical mechanical planarization of a copper-containing substrate affords high copper removal rates and low dishing values during CMP processing of the copper-containing substrate, including an abrasive, at least three surfactants, preferably non-ionic and preferably three distinct surfactants, preferably in the range of 100 ppm to 2000 ppm per surfactant and an oxidizing agent.