Patents Examined by Maki Angadi
  • Patent number: 8771540
    Abstract: The present disclosure provides a concentrate for use in chemical mechanical polishing slurries, and a method of diluting that concentrate to a point of use slurry. The concentrate comprises abrasive, complexing agent, and corrosion inhibitor, and the concentrate is diluted with water and oxidizer. These components are present in amounts such that the concentrate can be diluted at very high dilution ratios, without affecting the polishing performance.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: July 8, 2014
    Assignee: Fujifilm Planar Solutions, LLC
    Inventors: Hyungjun Kim, Richard Wen, Bin Hu, Minae Tanaka, Deepak Mahulikar
  • Patent number: 8772172
    Abstract: A semiconductor device manufacturing method includes a plasma etching step for etching an etching target film formed on a substrate accommodated in a processing chamber. In the plasma etching step, a processing gas including a gaseous mixture containing predetermined gases is supplied into the processing chamber, and a cycle including a first step in which a flow rate of at least one of the predetermined gases is set to a first value during a first time period and a second step in which the flow rate thereof is set to a second value that is different from the first value during a second time period is repeated consecutively at least three times without removing a plasma. The first time period and the second time period are set to about 1 to 15 seconds.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: July 8, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Masato Kushibiki, Eiichi Nishimura
  • Patent number: 8764993
    Abstract: A method of making a porous SiOC membrane is provided. The method comprises disposing a SiOC layer on a porous substrate, and etching the SiOC layer to form through pores in the SiOC layer. A porous SiOC membrane having a network of pores extending through a thickness of the membrane is provided.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: July 1, 2014
    Assignee: General Electric Company
    Inventors: Atanu Saha, Salil Mohan Joshi, An-Ping Zhang
  • Patent number: 8765002
    Abstract: A substrate processing apparatus includes a first processing chamber and a second processing chamber, a first substrate holding unit that holds a substrate in the first processing chamber, a chemical solution supply unit that supplies a chemical solution containing an etching component and a thickening agent to the substrate held by the first substrate holding unit, a substrate transfer unit that transfers the substrate from the first processing chamber to the second processing chamber in a state in which the chemical solution is held on the substrate, and a second substrate holding unit that holds a plurality of substrates on each of which the chemical solution is held in the second processing chamber.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 1, 2014
    Assignees: Mitsubishi Gas Chemical Company, Inc., Dainippon Screen Mfg. Co., Ltd.
    Inventors: Tomoyuki Azuma, Kenji Yamada, Hiroyuki Araki, Koji Ando
  • Patent number: 8758634
    Abstract: Disclosed is a composition for and applying said method for micro etching of copper or copper alloys during manufacture of printed circuit boards. Said composition comprises a copper salt, a source of halide ions, a buffer system and a benzothiazole compound as an etch refiner. The inventive composition and method is especially useful for manufacture of printed circuit boards having structural features of ?100 ?m.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: June 24, 2014
    Assignee: Atotech Deutschland GmbH
    Inventors: Dirk Tews, Christian Sparing, Martin Thoms
  • Patent number: 8753528
    Abstract: The present disclosure provides a chemical etchant which is capable of removing Ge and Ge-rich SiGe alloys in a controlled manner. The chemical etchant of the present disclosure includes a mixture of a halogen-containing acid, hydrogen peroxide, and water. Water is present in the mixture in an amount of greater than 90% by volume of the entire mixture. The present disclosure also provides a method of making such a chemical etchant. The method includes mixing, in any order, a halogen-containing acid and hydrogen peroxide to provide a halogen-containing acid/hydrogen peroxide mixture, and adding water to the halogen-containing acid/hydrogen peroxide mixture. Also disclosed is a method of etching a Ge or Ge-rich SiGe alloy utilizing the chemical etchant of the present application.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: June 17, 2014
    Assignees: International Business Machines Corporation, S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Stephen W. Bedell, Keith E. Fogel, Nicolas Daval
  • Patent number: 8747687
    Abstract: An aqueous CMP agent, comprising (A) solid polymer particles interacting and forming strong complexes with the metal of the surfaces to be polished; (B) a dissolved organic non-polymeric compound interacting and forming strong, water-soluble complexes with the metal and causing an increase of the material removal rate MRR and the static etch rate SER with increasing concentration of the compound (B); and (C) a dissolved organic non-polymeric compound interacting and forming slightly soluble or insoluble complexes with the metal, which complexes are capable of being adsorbed by the metal surfaces, and causing a lower increase of the MRR than the compound (B) and a lower increase of the SER than the compound (B) or no increase of the SER with increasing concentration of the compound (C); a CMP process comprising selecting the components (A) to (C) and the use of the CMP agent and process for polishing wafers with ICs.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: June 10, 2014
    Assignee: BASF SE
    Inventors: Vijay Immanuel Raman, Ilshat Gubaydullin, Yuzhuo Li, Mario Brands, Yongqing Lan
  • Patent number: 8741168
    Abstract: According to one embodiment, an etching method includes: supplying an etching-resistant material; and etching the silicon nitride film. The supplying includes supplying the etching-resistant material to a processing surface including a surface of a silicon nitride film and a surface of a non-etching film, the non-etching film including a material different from the silicon nitride film. The etching includes etching the silicon nitride film using an etchant in a state of the etching-resistant material being formed relatively more densely on the surface of the non-etching film than on the surface of the silicon nitride film.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhito Yoshimizu, Hisashi Okuchi, Hiroshi Tomita
  • Patent number: 8734666
    Abstract: A method for preparing nanotubes by providing nanorods of a piezoelectric material having an asymmetric crystal structure and by further providing hydroxide ions to the nanorods to etch inner parts of the nanorods to form the nanotubes.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: May 27, 2014
    Assignees: Samsung Electronics Co., Ltd., Kumoh National Institute of Technology
    Inventors: Jaeyoung Choi, Sangwoo Kim
  • Patent number: 8735299
    Abstract: There is provided a semiconductor device manufacturing method for forming a step-shaped structure in a substrate by etching the substrate having thereon a multilayer film and a photoresist film on the multilayer film and serving as an etching mask. The multilayer film is formed by alternately layering a first film having a first permittivity and a second film having a second permittivity different from the first permittivity. The method includes a first process for plasma-etching the first film by using the photoresist film as a mask; a second process for exposing the photoresist film to hydrogen-containing plasma; a third process for trimming the photoresist film; and a fourth process for etching the second film by using the trimmed photoresist film and the plasma-etched first film as a mask. The step-shaped structure is formed in the multilayer film by repeatedly performing the first process to the fourth process in this sequence.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: May 27, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Seiichi Watanabe, Manabu Sato, Kazuki Narishige, Takanori Sato, Takayuki Katsunuma
  • Patent number: 8735291
    Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: May 27, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Akiteru Ko
  • Patent number: 8721901
    Abstract: Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Gurtej S. Sandhu
  • Patent number: 8722541
    Abstract: A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chih-Han Lin
  • Patent number: 8715520
    Abstract: There is provided a substrate processing method capable of etching a layer containing, at least, platinum without using a halogen gas. When etching the platinum-manganese layer on a wafer W by using a tantalum (Ta) layer 38 having a certain pattern shape, a processing gas containing, at least, a carbon monoxide gas, a hydrogen gas, and a rare gas is used, and a ratio of a gas flow rate of the hydrogen gas to a total gas flow rate of the carbon monoxide gas and the hydrogen gas is in a range of from about 50% to about 75%.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: May 6, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Takashi Sone, Eiichi Nishimura
  • Patent number: 8709952
    Abstract: Provided is an etching method capable of etching even a silicon film that is included in a multi-layered structure by using a resist film or an organic film as a mask, and also capable of integrally etching the silicon film and a silicon oxide film disposed under the silicon film. The etching method which etches the multi-layered structure including the silicon oxide film and the silicon film formed on the silicon oxide film, includes: integrally etching the silicon film and the silicon oxide film included in the multi-layered structure by using a resist film or an organic film as an etching mask and using an etching gas containing a CH2F2 gas as an etching gas, when the silicon film and the silicon oxide film in the multi-layered structure are etched.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: April 29, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Aki Akiba
  • Patent number: 8709264
    Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christopher V. Jahnes, Anthony K. Stamper
  • Patent number: 8702998
    Abstract: A novel method to manufacture a flexible cable for a disk drive is disclosed. The method includes providing a flexible laminar sheet. The flexible laminar sheet has a dielectric substrate layer and an electrically conductive layer contacting a first side of the dielectric substrate layer. A portion of the electrically conductive layer is etched away to define a first plurality of electrically conductive traces and to expose an etched surface of the first side of the dielectric substrate layer. A second plurality of electrically conductive traces is deposited on the etched surface of the first side of the dielectric substrate layer.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: April 22, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Albert J. Guerini
  • Patent number: 8697581
    Abstract: A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: April 15, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Paul Bridger
  • Patent number: 8696918
    Abstract: Some embodiments include methods of forming patterns. A block copolymer film may be formed over a substrate, with the block copolymer having an intrinsic glass transition temperature (Tg,O) and a degradation temperature (Td). A temperature window may be defined to correspond to temperatures (T) within the range of Tg,O?T?Td. While the block copolymer is in the upper half of the temperature window, solvent may be dispersed into the block copolymer to a process volume fraction that induces self-assembly of the block copolymer into a pattern. A defect specification may be defined, and the process volume fraction of solvent may be at level that achieves self-assembly within the defect specification. In some embodiments, the solvent may be removed from within the block copolymer while maintaining the defect specification.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: April 15, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Dan Millward, Scott Sills
  • Patent number: 8697577
    Abstract: A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low dishing and erosion levels during CMP processing.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 15, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Xiaobo Shi, Bentley J. Palmer, Rebecca A. Sawayda