Patents Examined by Maki Angadi
  • Method of manufacturing a semiconductor device
    Patent number: 9105584
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first line pattern comprising a first film above an underlying layer, depositing a second film on a sidewall and a top surface of the first line pattern of the first film, etching the second film to eliminate the second film on the top surface of the first line pattern of the first film and leave the second film on the sidewall of the first line pattern of the first film, and removing the first line pattern to form a second line pattern of the second film above the underlying layer. The depositing the second film, etching the second film, and removing the first line pattern are sequentially performed within the same plasma processing device.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: August 11, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Omura, Toshiyuki Sasaki, Tsubasa Imamura, Kazuhisa Matsuda
  • Methods of utilizing block copolymer to form patterns
    Patent number: 9096730
    Abstract: Some embodiments include methods of forming patterns. A block copolymer film may be formed over a substrate, with the block copolymer having an intrinsic glass transition temperature (Tg,0) and a degradation temperature (Td). A temperature window may be defined to correspond to temperatures (T) within the range of Tg,0?T?Td. While the block copolymer is in the upper half of the temperature window, solvent may be dispersed into the block copolymer to a process volume fraction that induces self-assembly of the block copolymer into a pattern. A defect specification may be defined, and the process volume fraction of solvent may be at level that achieves self-assembly within the defect specification. In some embodiments, the solvent may be removed from within the block copolymer while maintaining the defect specification.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dan Millward, Scott E. Sills
  • Method for forming copper wiring
    Patent number: 9101067
    Abstract: In a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess which is formed in a substrate in a predetermined pattern, a barrier film formed of a TaAlN film is formed at least on the surface of the recess by thermal ALD or thermal CVD. Then a Cu film is formed to fill the recess with the Cu film. Further, the Cu wiring is formed in the recess by polishing the entire surface of the substrate by CMP.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 4, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Toshio Hasegawa
  • Metal structural body-containing polymer film, method for manufacturing metal structural body-containing polymer film, and method for manufacturing patterned structural body
    Patent number: 9096936
    Abstract: A method for manufacturing a patterned structural body by which a patterned structural body having a micropattern can be manufactured, a metal structural body-containing polymer film that can be used in the manufacture of the patterned structural body, and a method for manufacturing the polymer film are provided. The metal structural body-containing polymer film comprises a polymer film that includes a block copolymer having an ion-conductive segment and a non-ion-conductive segment and has a microphase-separated structure including ion-conductive domains and non-ion-conductive domains, and a metal structural body localized at the ion-conductive domains.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: August 4, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Wataru Kubo, Kazuhiro Yamauchi, Kenji Yamada, Mamiko Kumagai, Kyoko Kumagai, Toshiki Ito, Norishige Kakegawa
  • Methods for selectively coating three-dimensional features on a substrate
    Patent number: 9093323
    Abstract: Methods here disclosed provide for selectively coating three-dimensional features on a substrate while avoiding liquid coating material wicking into micro cavities on the substrates. The steps include depositing a semiconductor layer on a sacrificial layer formed on a template and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating three-dimensional features on the substrate using a liquid coating step for applying a liquid coating material to a pre-determined surface of the three-dimensional features on the substrate.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: July 28, 2015
    Assignee: Solexel, Inc.
    Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi, Somnath Nag
  • Plasma processing method and plasma processing apparatus
    Patent number: 9087676
    Abstract: A plasma processing method includes forming a silicon oxide film on a surface of a member provided within a chamber with plasma of a silicon-containing gas without oxygen while controlling a temperature of the member to be lower than a temperature of another member; performing a plasma process on a target object loaded into the chamber with plasma of a processing gas after the silicon oxide film is formed on the surface of the member; and removing the silicon oxide film from the surface of the member with plasma of a fluorine-containing gas after the target object on which the plasma process is performed is unloaded to an outside of the chamber.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: July 21, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takayuki Katsunuma, Masanobu Honda, Hironobu Ichikawa
  • Polishing agent and polishing method
    Patent number: 9085714
    Abstract: A polishing agent for polishing a non-oxide single-crystal substrate such as a silicon carbide single-crystal substrate with a high polishing rate to obtain a smooth surface is provided. This polishing agent comprises an oxidant having redox potential of 0.5 V or more and containing a transition metal, silicon oxide particles, cerium oxide particles and a dispersion medium, in which a mass ratio of the silicon oxide particles to the cerium oxide particles is from 0.2 to 20.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: July 21, 2015
    Assignee: ASAHI GLASS COMPANY, LIMITED
    Inventors: Iori Yoshida, Satoshi Takemiya, Hiroyuki Tomonaga
  • Methods for etching a workpiece, an apparatus configured to etch a workpiece, and a non-transitory computer readable medium
    Patent number: 9079210
    Abstract: A method for etching a workpiece may be provided, which may include: determining a plurality of reference etch profiles for a plurality of positions of an etchant dispenser, each reference etch profile corresponding to a respective position of the plurality of positions of the etchant dispenser; determining a thickness profile of the workpiece; determining a respective etch duration for each position of the plurality of positions of the etchant dispenser based on the determined thickness profile and the plurality of reference etch profiles, to reduce a total thickness variation of the workpiece; and dispensing an etchant over the workpiece via the etchant dispenser for the determined respective etch duration for each position of the plurality of positions.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: July 14, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Karl Pilch, Sonja Muringer
  • Methods for obtaining hollow nano-structures
    Patent number: 9067242
    Abstract: Methods are provided for obtaining hollow nano-structures which include the steps of providing a suspended film starting layer on a support substrate, depositing on the starting layer a sacrificial layer, performing, in progressive sequence, a complete erosion phase of said support substrate and starting layer and performing an at least partial erosion phase of the sacrificial layer previously deposited on the starting layer so as to obtain holes passing through the starting layer and passing or non passing through the sacrificial layer, depositing, on the side of the support substrate opposite to that where the starting layer is put, at least one covering layer arranged to internally cover the holes created by the progressive erosion. Hollow nano-structures formed by such methods are also provided.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: June 30, 2015
    Assignee: Fondazione Istituto Italiano di Tecnologia
    Inventors: Francesco De Angelis, Enzo Di Fabrizio
  • Etching liquid composition and etching method
    Patent number: 9068267
    Abstract: The etching liquid composition of the present invention contains a ferric ion component; a hydrogen chloride component; and a component that is at least one type of compound selected from the group consisting of a compound represented by general formula (1) below and a straight chain or branched chain alcohol having 1 to 4 carbon atoms: wherein R1 and R3 are each independently a hydrogen atom or a straight chain or branched chain alkyl group having 1 to 4 carbon atoms, R2 is a straight chain or branched chain alkylene group having 1 to 4 carbon atoms, and n is a number between 1 and 3.
    Type: Grant
    Filed: December 25, 2012
    Date of Patent: June 30, 2015
    Assignee: Adeka Corporation
    Inventors: Yuta Taguchi, Kouta Saitoh
  • Aspect ratio dependent etch (ARDE) lag reduction process by selective oxidation with inert gas sputtering
    Patent number: 9064812
    Abstract: Embodiments of methods for etching a substrate include exposing the substrate to a first plasma formed from an inert gas; exposing the substrate to a second plasma formed from an oxygen-containing gas to form an oxide layer on a bottom and sides of a low aspect ratio feature and a high aspect ratio feature, wherein the oxide layer on the bottom of the low aspect ratio feature is thicker than on the bottom of the high aspect ratio feature; etching the oxide layer from the bottom of the low and high aspect ratio features with a third plasma to expose the bottom of the high aspect ratio feature while the bottom of the low aspect ratio feature remains covered; and exposing the substrate to a fourth plasma formed from a halogen-containing gas to etch the bottom of the low aspect ratio feature and the high aspect ratio feature.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: June 23, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jinsu Kim, Xiaosong Ji, Jinhan Choi, Ho Jeong Kim, Byungkook Kong, Hoon Sang Lee
  • Method and apparatus for controlling substrate DC-bias and ion energy and angular distribution during substrate etching
    Patent number: 9053908
    Abstract: A variable capacitor is provided within a radiofrequency (RF) power transmission path to a bias electrode, in addition to an impedance matching circuit provided within the RF power transmission path to the bias electrode. An RF power supply is operated in a pulsed mode to transmit pulses of RF power through the RF power transmission path to the bias electrode. A capacitance of the variable capacitor is set to control a rate at which a DC bias voltage builds up on a substrate present above the bias electrode during each pulse of RF power. The rate at which the DC bias voltage builds up on the substrate controls an ion energy distribution and an ion angular distribution within a plasma exposed to an electromagnetic field emanating from the substrate.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: June 9, 2015
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Alexander Paterson
  • Method of manufacturing a graphene monolayer on insulating substrates
    Patent number: 9023220
    Abstract: A method of manufacturing a graphene monolayer on insulating substrates from CVD graphene synthesis, comprising: applying a thermal release adhesive tape to the bottom graphene layer deposited at the bottom of the metal foil in the CVD graphene synthesis, detaching the thermal release adhesive tape and the bottom graphene layer from the metal foil via the application of heat, from 1° C. up to 5° C. higher than the release temperature of the thermal release adhesive tape so that the thermal release adhesive tape with the bottom graphene layer can be removed, obtaining a metal foil with a top graphene layer sample, and transferring the top graphene layer onto a substrate via a sacrificial protective layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 5, 2015
    Assignee: Graphenea, S.A.
    Inventors: Amaia Zurutuza Elorza, Alba Centeno Perez, Beatriz Alonso Rodriguez, Amaia Pesquera Rodriguez
  • Radical-component oxide etch
    Patent number: 9023734
    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a nitrogen-and-hydrogen-containing precursor. Reactants thereby produced etch the patterned heterogeneous structures with high silicon oxide selectivity while the substrate is at high temperature compared to typical Siconi™ processes. The etch proceeds without producing residue on the substrate surface. The methods may be used to remove silicon oxide while removing little or no silicon, polysilicon, silicon nitride or titanium nitride.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Jingchun Zhang, Ching-Mei Hsu, Seung Park, Anchuan Wang, Nitin K. Ingle
  • Etching method using an at least semi-solid media
    Patent number: 9011707
    Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Darwin Rusli
  • Method for manufacturing silicon carbide semiconductor device
    Patent number: 9005462
    Abstract: In a method for manufacturing a silicon carbide semiconductor device, a conductive layer is formed on a silicon carbide layer. The silicon carbide layer and the conductive layer react with each other thus forming an alloy layer formed of a reaction layer in contact with the silicon carbide layer and a silicide layer on the reaction layer. A carbon component is removed from the silicide layer. A portion of the silicide layer is removed using an acid thus exposing at least a portion of the reaction layer. An electrode layer is formed on an upper side of the exposed reaction layer.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: April 14, 2015
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventor: Jun-ichi Ohno
  • Etching solution capable of effectively reducing galvanic effect
    Patent number: 8999194
    Abstract: The present invention is to provide an etching solution capable of effectively reducing Galvanic effect, wherein the etching solution is obtained by way of dissolving an etchant and a nitrogen containing five-member heterocyclic compound in water. Thus, when at least one first metal (e.g., gold) and at least one second metal (e.g., copper) disposed on a substrate is treated with a wet etching process by using this etching solution, the nitrogen containing five-member heterocyclic compound would form an organic protecting film on the first metal having higher reduction potential, so as to effectively avoid the second metal from being over etched resulted from the Galvanic effect.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: April 7, 2015
    Assignee: E-Chem Enterprise Corp.
    Inventors: Cheng-Ying Tsai, Cheng-Kai Liao, Su-Fei Hsu
  • Method to reduce dielectric constant of a porous low-k film
    Patent number: 8993444
    Abstract: Embodiments of the present invention generally relate to methods for lowering the dielectric constant of low-k dielectric films used in semiconductor fabrication. In one embodiment, a method for lowering the dielectric constant (k) of a low-k silicon-containing dielectric film, comprising exposing a porous low-k silicon-containing dielectric film to a hydrofluoric acid solution and subsequently exposing the low-k silicon-containing dielectric film to a silylation agent. The silylation agent reacts with Si—OH functional groups in the porous low-k dielectric film to increase the concentration of carbon in the low-k dielectric film.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: March 31, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Kelvin Chan, Jin Xu, Kang Sub Yim, Alexandros T. Demos
  • Evaluation of etching conditions for pattern-forming film
    Patent number: 8992788
    Abstract: In conjunction with a photomask blank comprising a transparent substrate, a pattern-forming film, and an etch mask film, a set of etching conditions for the pattern-forming film is evaluated by measuring a first etching clear time (C1) taken when the etch mask film is etched under the etching conditions to be applied to the pattern-forming film, measuring a second etching clear time (C2) taken when the pattern-forming film is etched under the etching conditions, and computing a ratio (C1/C2) of the first to second etching clear time.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: March 31, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shinichi Igarashi, Hiroki Yoshikawa, Yukio Inazuki, Hideo Kaneko
  • Hydrogen plasma cleaning of germanium oxide surfaces
    Patent number: 8987143
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: March 24, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ratsamee Limdulpaiboon, Chi-I Lang, Sandip Niyogi, J. Watanabe