Patents Examined by Mano Padmanabhan
  • Patent number: 10802740
    Abstract: A method includes: storing a first data extent on a physical medium, wherein the physical medium is divided into a plurality of storage blocks, wherein each of the storage blocks has a size that is different than a size of the first data extent, further wherein the first data extent is stored to a first block of the plurality of storage blocks; generating a descriptor for the first data extent, wherein the descriptor indicates that the first data extent starts within the first block of the plurality of blocks and indicates an offset from the beginning of the first block at which the first data extent starts; and storing the descriptor within the first block.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: October 13, 2020
    Assignee: NETAPP, INC.
    Inventors: Randolph Sterns, Charles Binford, William P. Delaney, Joseph Blount, Reid Kaufmann, Joseph Moore
  • Patent number: 10796769
    Abstract: The present disclosure relates to a memory device and a memory system having the same. The memory device includes page buffers arranged in a first direction and a second direction perpendicular to the first direction, a first storage group and a second storage group arranged adjacent to the page buffers in the second direction, and a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines according to a number of page buffers and a number of first and second storage groups.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang Hwan Kim, Min Su Kim, Kyeong Min Chae
  • Patent number: 10795614
    Abstract: In a memory controller for controlling an operation of a memory device, the memory controller includes a buffer memory and a buffer management circuit. The buffer memory includes an input buffer for storing input data received from a host and an output buffer for storing output data received from the memory device. The buffer management circuit changes capacities of the input buffer and the output buffer, based on a use state of at least one of the input buffer and the output buffer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventor: Ho Jung Yun
  • Patent number: 10789166
    Abstract: A computer system acquires information on a first present input subset selected from first present input data for a first step from a run-time log of the first step, determines whether or not first cache data corresponding to the first present input subset for the first step is present in a cache area with reference to management information, and determines the first cache data as present output data for the first present input data in a case where the first cache data is present.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: September 29, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Cheng Luo, Machiko Asaie, Keiro Muro
  • Patent number: 10776014
    Abstract: Some embodiments can include a system. In some embodiments, a system can comprise one or more processors and one or more non-transitory storage devices storing computing instructions configured to run on the one or more processors and perform acts.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: September 15, 2020
    Assignee: WALMART APOLLO, LLC
    Inventors: Charandeep Sehgal, Vikas Bhat, Ganesh Krishnan, Venkatesh Kandaswamy
  • Patent number: 10779147
    Abstract: Systems and methods for vendor-agnostic access to non-volatile memory of a wireless memory tag include: detecting, via a wireless memory host, a wireless memory tag; providing a vendor-agnostic command to the wireless memory tag to affect a change in a register-based interface of the wireless memory tag, wherein the change results in reading data from non-volatile memory of the wireless memory tag, writing data to the non-volatile memory of the wireless memory tag, or both.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Danilo Caraccio
  • Patent number: 10776049
    Abstract: a memory system may include: a memory device including a plurality of memory blocks; and a controller configured to manage the plurality of memory blocks as a plurality of super blocks, the controller may classify and may manage super blocks formed by mixing and grouping at least one bad memory block and normal memory blocks as first super blocks, and may classify and may manage super blocks formed by grouping only normal memory blocks as second super blocks, the controller may check an accumulated size of write data received from a host, may group the write data into a plurality of data groups based on a result of the checking of the accumulated size, and may store, each time one data group is formed, the formed one data group in N first super blocks and M second super blocks.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Se-Hyun Kim
  • Patent number: 10761748
    Abstract: A method for performing a write operation in a distributed storage system is disclosed. The method comprises receiving a first time-stamped write request from a proxy server. Further, the method comprises determining if the first time-stamped write request is within a time window of a reorder buffer and if the first time-stamped write request overlaps with a second time-stamped write request in the reorder buffer. Responsive to a determination that the first time-stamped write request is outside the time window or that the first time-stamped write request is within the time window but has an older time-stamp than the second time-stamped write request, the method comprises rejecting the first time-stamped write request. Otherwise, the method comprises inserting the first time-stamped write request in the reorder buffer in timestamp order and transmitting an accept to the proxy server.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: September 1, 2020
    Assignee: DATERA, INCORPORATED
    Inventor: Guillermo J. Rozas
  • Patent number: 10761942
    Abstract: To perform Recovery Point Objective (RPO) driven backup scheduling, the illustrative data storage management system is enhanced in several dimensions, including an illustrative enhanced data agent and an illustrative enhanced storage manager. Illustrative enhancements include: streamlining the user interface to take in fewer parameters; backup job scheduling is largely automated based on several factors, and includes automatic backup level conversion for legacy systems; backup job priorities are dynamically adjusted to re-submit failed data objects with an “aggressive” schedule in time to meet the RPO; only failed items are resubmitted for failed backup jobs.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 1, 2020
    Assignee: Commvault Systems, Inc.
    Inventors: Bhavyan Bharatkumar Mehta, Anand Vibhor, Amey Vijaykumar Karandikar, Gokul Pattabiraman, Hemant Mishra
  • Patent number: 10761764
    Abstract: A storage system includes at least one drive chassis connected to at least one host computer via a first network, and a storage controller connected to the drive chassis, in which the storage controller instructs the drive chassis to create a logical volume, and the drive chassis creates a logical volume according to an instruction from the storage controller, provides a storage area of the storage system to the host computer, and receives an IO command from the host computer to the storage area of the storage system.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 1, 2020
    Assignee: HITACHI, LTD.
    Inventors: Hirotoshi Akaike, Koji Hosogi, Norio Shimozono, Sadahiro Sugimoto, Nobuhiro Yokoi
  • Patent number: 10754729
    Abstract: To perform Recovery Point Objective (RPO) driven backup scheduling, the illustrative data storage management system is enhanced in several dimensions. Illustrative enhancements include: streamlining the user interface to take in fewer parameters; backup job scheduling is largely automated based on several factors, and includes automatic backup level conversion for legacy systems; backup job priorities are dynamically adjusted to re-submit failed data objects with an “aggressive” schedule in time to meet the RPO; only failed items are resubmitted for failed backup jobs.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: August 25, 2020
    Assignee: Commvault Systems, Inc.
    Inventors: Bhavyan Bharatkumar Mehta, Anand Vibhor, Amey Vijaykumar Karandikar, Gokul Pattabiraman, Hemant Mishra
  • Patent number: 10754556
    Abstract: Prioritizing virtual volumes to take offline in a thin provisioning system with garbage collection. The method categorizes virtual volumes based on garbage collection properties of their write behavior and adds metadata indicating a category of a virtual volume. The method schedules virtual volumes to be taken offline by predicting virtual volume space utilization of active virtual volumes for a defined time period in combination with estimated garbage collection in that period to determine a need to take virtual volumes offline. The method selects virtual volumes to take offline by their category to ensure that the virtual volumes producing the most garbage collection unfriendly workloads are taken offline first.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Miles Mulholland, Ben Sasson, Gordon Hutchison, Lee J. Sanders
  • Patent number: 10754564
    Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeon-kyu Choi, Ki-seok Oh, Seung-jun Shin, Hye-ran Kim
  • Patent number: 10754559
    Abstract: A first storage system is configured to participate in a replication process with a second storage system using an active-active configuration. A request for a time-to-live (TTL) grant is received in the first storage system from the second storage system. The first storage system computes an estimate of a difference between local times in the respective first and second storage systems, utilizes the computed estimate in the first storage system to determine a TTL expiration time in the local time in the second storage system, and sends the TTL grant with the TTL expiration time to the second storage system in response to the request. The computed estimate of the difference between the local times in the respective first and second storage systems is illustratively utilized in the first storage system to determine a range for the local time in the second storage system.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: August 25, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: David Meiri, Anton Kucherov
  • Patent number: 10747667
    Abstract: An aspect of memory management is provided. An aspect includes evaluating performance parameters of caches of a control module. The caches of the control module have two types of entries: address, hash, and physical location values, and address-to-short-hash (A2SH) values. An aspect further includes evaluating performance parameters of caches of a data module of the multi-layer cache system. The caches of the data module cache include three types of entries: a short-hash-to-physical address, a full-hash-and-short-hash-to-physical address, and a filter mechanism. An aspect further includes predicting an effect that a modification to a size of one of the caches o is on performance of operations at the multi-level cache based on results of the calculating the performance parameters of the caches. Upon estimating an increase in performance, an aspect includes increasing allocation to the cache is determined to have increased performance responsive to the estimating, and decreasing allocation from another cache.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Assaf Natanzon, Amitai Alkalay, Zvi Schneider
  • Patent number: 10747455
    Abstract: Example peer storage systems, storage devices, and methods provide peer operation state indicators for managing peer-to-peer operations. Peer storage devices establish peer communication channels that communicate data among the peer storage devices that bypasses the storage control plane for managing the peer storage devices. The peer storage devices identify peer operations that communicate data through the peer communication channels and generate a peer operation state during the operating period of the peer operations. The peer storage devices activate a state indicator configured to indicate the peer operation state. The state indicator may be used to prevent a storage controller or other entity with access to the storage device, including administrative personnel, from performing an operation that may corrupt data or truncate a media operation involving peer-to-peer communications.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Adam Roberts
  • Patent number: 10747466
    Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Puneet Sabbarwal, Indu Prathapan
  • Patent number: 10740024
    Abstract: In one aspect, runtime feature overhead minimization is provided for a storage system. An aspect includes providing a system table having features available to the system and a field indicating whether a feature is enabled. An aspect also includes providing a configuration table for data modules in the system that includes features available to storage units managed by the data modules and a field that indicates whether a feature is enabled for a storage unit. Upon receiving a request that includes a selected storage unit, the data modules access the system table. For each feature in the system table, the data modules determine whether the feature is set to enabled via the corresponding flag field. Upon determining the feature is set to disabled via the corresponding flag field in the system table, performing an operation identified in the request without accessing the configuration table.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: August 11, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Xiangping Chen, Anton Kucherov
  • Patent number: 10732906
    Abstract: Apparatus and method for managing data in a multi-device data storage system. In some embodiments, a plurality of data storage devices are provided, each data storage device having a local driver circuit adapted to transfer data with a local memory module. A main driver circuit external to the plurality of data storage devices is configured to stream frequency modulated write data via parallel data transfer paths to the respective local driver circuits for concurrent transfer of the frequency modulated write data to the respective local memory modules.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 4, 2020
    Assignee: Seagate Technology LLC
    Inventors: Philip Jurey, Dale T. Riley, John W. Shaw
  • Patent number: 10733096
    Abstract: A method for implementing a shared memory buffer includes at an apparatus comprising a processor and a physical memory, running a host environment with a host virtual memory. The method further includes running a guest environment with a guest virtual memory, performing, by the host environment, an allocation of a frame buffer in the physical memory, and mapping the allocated frame buffer into the host virtual memory. Additionally, the method includes passing a handle of the allocated frame buffer to the guest environment and performing a mapping of the allocated frame buffer into the guest virtual memory, the mapping based on the handle of the allocated frame buffer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ivan Getta, Sudhi Herle, Ahmed M. Azab, Rohan Bhutkar, Guruprasad Ganesh, Wenbo Shen