Abstract: A high-temperature protection method for a solid state drive (SSD) and an implementation device thereof are provided. The device includes a temperature measurement circuit, a host communication interface, a SSD main controller and NAND Flash storage medium chips, wherein the SSD main controller is for controlling data transmission and command interaction between a host and the NAND Flash storage medium chips, including a SATA/PCIe (serial advanced technology attachment/peripheral component interconnect express) physical controller, a high-temperature control manager, a main controller core, a RAM (random access memory) and a NAND Flash controller.

Abstract: An embodiment of a semiconductor package apparatus may include technology to create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory, identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and set a flag in the tracking structure to indicate that the memory location had the identified write request. Other embodiments are disclosed and claimed.

Abstract: A data access method, a routing apparatus, and a storage system are provided. The method is applied to a storage system including a first storage device, a second storage device, and a routing apparatus. A logical unit in each storage device includes at least one first-type logical block and at least one second-type logical block. According to the method, when sending access requests to the storage devices in the storage system according to a preset rule, the routing apparatus sends access requests corresponding to same target logical blocks to one of the storage devices according to a preset rule. This reduces network overheads between the storage system and the application server, and improves efficiency of processing the access requests by the storage system.

Abstract: In one embodiment, a safe data commit process manages the allocation of task control blocks (TCBs) as a function of the type of task control block (TCB) to be allocated for destaging and as a function of the identity of the RAID storage rank to which the data is being destaged. For example, the allocation of background TCBs is prioritized over the allocation of foreground TCBs for destage operations. In addition, the number of background TCBs allocated to any one RAID storage rank is limited. Once the limit of background TCBs for a particular RAID storage rank is reached, the distributed safe data commit logic switches to allocating foreground TCBs. Further, the number of foreground TCBs allocated to any one RAID storage rank is also limited. Other features and aspects may be realized, depending upon the particular application.

Abstract: A system and method of avoiding loss of memory trace data, including monitoring a first-in-first-out (FIFO) buffer to determine if the FIFO buffer has overflowed due to memory access, determining whether an overflow of the FIFO buffer is acceptable, changing an operating mode of a target system if overflow of the FIFO buffer is unacceptable to avoid FIFO buffer overflow, and collecting memory trace data on the memory accesses.

Abstract: Techniques perform storage management. Such techniques involve, in response to an operation to be performed on data in a cache page, determining a first cache page reference corresponding to the cache page, the first cache page reference comprising a pointer value indicating the cache page. Such techniques further involve creating, based on the first cache page reference and the operation, a second cache page reference corresponding to the cache page, the second cache page reference comprising the pointer value. Such techniques further involve performing the operation on the data in the cache page via the second cache page reference. One cache page can correspond to a plurality of cache page references. Additionally, copy of data from one cache page to a further cache page can be effectively avoided, so as to enhance input/output performance and utilization rate of storage space.

Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

Abstract: According to one embodiment, a memory system includes a cache configured to cache a part of a multi-level mapping table for logical-to-physical address translation, and a controller. The multi-level mapping table includes a plurality of hierarchical tables corresponding to a plurality of hierarchical levels. The table of each hierarchical level includes a plurality of address translation data portions. The controller sets a priority for each of the hierarchical level based on a degree of bias of reference for each of the hierarchical level, and preferentially caches each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with low priority.

Abstract: Techniques for virtual proxy based backup of virtual machines in a cluster environment are disclosed. In some embodiments, each of a subset of virtual machines hosted by physical nodes in a cluster environment is configured as a virtual proxy dedicated to backup operations. During backup, data rollover of each virtual machine in the cluster environment that is subjected to backup is performed using a virtual proxy.

Abstract: Systems and methods are disclosed for die access order variation to a memory having a multiple-die architecture. In certain embodiments, an apparatus may comprise a controller configured to assign a unique die access order to each set of multiple sets of related commands, a die access order controlling an order in which a plurality of dies of a solid state memory are accessed to perform the related commands. A first stream may be assigned a first die access order, and a second stream may be assigned a second, different die access order, thereby distributing the timing of die access collisions between the streams.

Abstract: A flash memory storage device including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of well regions. Each of the well regions includes a plurality of memory blocks and a record block. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to perform an erase operation on the memory blocks of each of the well regions and record erase times of each of the well regions into the respective record block. In addition, a method for operating a flash memory storage device is also provided.

Abstract: Hash-based application programming interface (API) importing can be prevented by allocating a name page and a guard page in memory. The name page and the guard page being associated with (i) an address of names array, (ii) an address of name ordinal array, and (iii) an address of functions array that are all generated by an operating system upon initiation of an application. The name page can then be filled with valid non-zero characters. Thereafter, protections on the guard page can be changed to no access. An entry is inserted into the address of names array pointing to a relative virtual address corresponding to anywhere within the name page. Access to the guard page causes the requesting application to terminate. Related apparatus, systems, techniques and articles are also described.

Abstract: Disclosed in some examples are methods, systems, machine-readable mediums, and NAND devices which create logical partitions when requested to create a physical partition. The controller on the NAND mimics the creation of the physical partition to the host device that requested the physical partition. Thus, the host device sees the logical partition as a physical partition. Despite this, the NAND does not incur the memory storage expense of creating a separate partition, and additionally the NAND can borrow cells for overprovisioning from another partition. In these examples, a host device operating system believes that a physical partition has been created, but the NAND manages the memory as a contiguous pool of resources. Thus, a logical partition is created at the NAND memory controller level—as opposed to at the operating system level.

Abstract: A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract: A method, apparatus, system, and computer program product for managing a storage system. Data associated with a set of tags is identified by a computer system using a policy, wherein the policy defines the set of tags for a set of types of data used in a process performed in an organization using data in the storage system. A set of storage tiers for the data associated with the set of tags is determined by the computer system using the policy. The policy defines the set of storage tiers for the data associated with the set of tags when the data associated with the set of tags is used by the process. The data associated with the set of tags is moved by the computer system to the set of storage tiers as determined using the policy.

Abstract: A storage system includes a controller and a nonvolatile memory drive, in which the controller transmits a write request that designates a volume identifier of a volume to be provided to a host, to the nonvolatile memory drive; the nonvolatile memory drive exclusively allocates a free block selected from a plurality of blocks to the volume identifier; write data of the write request is written to the free block; when the write data is update write data, an area that stores data to be updated is changed to an invalid data area; and after valid data of a block including the invalid data area is migrated to another block, all data of the block including the invalid data area is erased.

Abstract: Examples include a processor including fetch circuitry to fetch a guest physical address translation instruction having a format with fields to specify at least an opcode and locations of a source vector and a destination vector, decode circuitry to decode the fetched guest physical address translation instruction, and execution circuitry to execute the decoded guest physical address translation instruction. Execution of the decoded guest physical address translation instruction includes comparing guest physical addresses of the source vector with base and end addresses of a selected memory region, masking a guest physical address of the source vector if the guest physical address is in the selected memory region, translating the masked guest physical addresses into host addresses, and storing the host addresses into the destination vector.

Abstract: A shack-sensor apparatus may include a sensor configured to detect a positional state of a hard-drive drawer. The shock-sensor apparatus may also include a mounting component coupled to the sensor and configured to mount the sensor in a location to monitor the positional state of the hard-drive drawer. In addition, the shock-sensor apparatus may include a computing module, electronically coupled to the sensor, that analyzes sensor data provided by the sensor to predict a shock event of the hard-drive drawer and send, in response to predicting the shock event, a signal to at least one hard drive in the hard-drive drawer to prevent damage to the hard drive. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.