Abstract: A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.

Abstract: A memory system having memory components and a processing device to: communicate with a host system to obtain, from the host system, at least one host specified parameter during booting up of the host system; execute first firmware to process requests from the host system using the at least one host specified parameter, the requests including storing data into the memory components and retrieving data from the memory components; install second firmware while running the first firmware; store the at least one host specified parameter; and reboot into executing the second firmware using the at least one host specified parameter, without rebooting of the host system.

Abstract: An information handling system includes a management interface that may detect a configuration change request for the flash dual in-line memory modules, and may determine whether the configuration change request is a hardware configuration change or a software configuration change. In response to the configuration change request being the software configuration change the management interface may re-configure flash dual in-line memory modules based on a first profile identified by the configuration change request without resetting the information handling system, update metadata for the flash dual in-line memory modules based on the first profile without resetting the information handling system, and update a dual in-line memory module firmware interface table for the flash dual in-line memory modules based on the first profile without resetting the information handling system.

Abstract: Provided are a computer program product, system, and method demote scan processing to demote tracks from cache. Tracks in the storage stored in the cache are indicated in a cache list. The cache list is scanned to determine unmodified tracks to initiate to demote. In response to processing an indicated modified track in the cache list while scanning the cache list, a destage is initiated for the processed indicated modified track and continuing to scan the cache list to determine unmodified tracks. In response to processing a number of modified tracks indicted in the cache list, a determination is made of an unmodified track in the cache list and continuing to scan, from the determined unmodified track, for unmodified tracks to initiate to demote.

Abstract: Embodiments of the present disclosure support implementation of a Level-1 (L1) cache in a microprocessor based on independently accessed data and tag arrays. Presented implementations of L1 cache do not require any stall pipeline mechanism for stalling execution of instructions, leading to improved microprocessor performance. A data array in the cache is interfaced with one or more data index queues that comprise, upon occurrence of a conflict between at least one instruction requesting access to the data array and at least one other instruction that accessed the data array, at least one data index for accessing the data array associated with the at least one instruction. A tag array in the cache is interfaced with a tag queue that stores one or more tag entries associated with one or more data outputs read from the data array based on accessing the data array.

Abstract: A storage system in one embodiment comprises a plurality of storage devices and a storage controller. The storage controller is configured to receive a plurality of logical addresses. Each logical address has one of a content-based mapping type and an address-based mapping type. Responsive to a first logical address of the plurality of logical addresses having the content-based mapping type, the storage controller is configured to utilize a content-based mapping generated based on content of a data page associated with the first logical address to identify a corresponding physical address. Responsive to a second logical address of the plurality of logical addresses having the address-based mapping type, the storage controller is configured to utilize an address-based mapping generated based on the second logical address to identify a corresponding physical address.

Abstract: A storage system includes at least one drive chassis connected to at least one host computer via a first network, and a storage controller connected to the drive chassis, in which the storage controller instructs the drive chassis to create a logical volume, and the drive chassis creates a logical volume according to an instruction from the storage controller, provides a storage area of the storage system to the host computer, and receives an IO command from the host computer to the storage area of the storage system.

Abstract: Systems and methods are disclosed to abort a command at a data storage controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a data storage controller configured to receive an abort indicator from a host device, generate an abort tracking indicator at a receiving unit configured to receive commands from the host device, monitor to determine when the selected command is received at the receiving unit based on the abort tracking indicator, and abort the selected command when the selected command is received at the receiving unit. In some embodiments, the data storage controller may generate an abort tracking indicator at a completion unit configured to notify the host device of completed commands, and monitor for the selected command at the completion unit based on the abort tracking indicator.

Abstract: In one example, a method for writing data includes receiving a write request and performing a first type of logging process in connection with the write request, and creating a corresponding first logging record. Additionally, a second type of logging process is performed in connection with the write request, and a corresponding second logging record created, where the second type of logging process is different from the first type of logging process. Next, a determination is made, as between the two logging records, which of the logging records requires the least amount of non-volatile random access memory (NVRAM), and the logging record that requires the least amount of NVRAM is written to the NVRAM.

Abstract: Embodiments of the present invention provide memory optimization by phase-dependent data residency. Application programs are profiled a priori or in real time for temporal memory usage. Memory regions such as initialization data are proactively removed from memory when the application transitions to a new phase. A hypervisor monitors application activity and coordinates the removal of memory regions that are no longer needed by the application. Additionally, memory regions that are anticipated to be needed in the future are proactively preloaded.

Abstract: A system and method for improving storage system operation is disclosed. A storage system includes a first tier with high-performance redundancy and a second tier with capacity efficient redundancy. The first tier and the second tier are built from the same storage devices in a storage pool so each storage device includes both the first and second tiers. The storage system stores write data initially to the first tier. When demand for the data falls below a threshold, the storage system migrates the write data to the second tier. This is done by changing the mapping of underlying physical locations on the storage devices where the write data is stored so that the underlying physical locations are logically associated with the second tier instead of the first tier. After remapping, the storage system also computes parity information for the migrated write data and stores it in the second tier.

Abstract: A method for storing a data segment in a storage tier of a storage unit comprising at least two storage tiers includes receiving the data segment to be stored including metadata; receiving metadata of data segments stored in the storage unit; and determining the storage tier to store the received data segment to and a protection level dependent on the metadata received and dependent on the metadata of the received data segment.

Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.

Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

Abstract: A computer-implemented method according to one embodiment includes sending, from a first system to a second system, a request for a clock value associated with a third system, receiving, from the second system, a clock value associated with the third system and a query clock value determined at the second system, comparing, at the first system, the clock value associated with the third system to the query clock value determined at the second system to determine whether the third system is unavailable, and performing one or more predetermined actions at the first system in response to determining that the third system is unavailable.

Abstract: A method and apparatus for capturing a snapshot of storage volumes of a data capture group are disclosed. In the method and apparatus, a request to create a data capture group may be received and processed. The data capture group may have one or more storage volumes. Upon defining the data capture group, a snapshot of the storage volumes of the data capture group may be taken.

Abstract: Data is stored in a non-volatile memory during an off-line transaction between a circuit containing memory and a terminal. A page of the memory is assigned to each transaction, and the data of each transaction is stored sequentially in the corresponding page. The page assigned to each transaction is locked in a write mode at the end of the corresponding transaction.

Abstract: A data processing system and method are disclosed. The data processing system may include a host, a storage device, and a battery supplying a power to the host and the storage device. The storage device may include a memory storing data received from the host, a cache temporarily storing the data, and a controller controlling the memory and the cache. The controller may be configured to receive a detachability attribute of the battery from the host, and determine, based on the detachability attribute of the battery, whether to perform a backup operation of the data in response to receiving a write command from the host.

Abstract: A method for write aggregation using a host memory buffer includes fetching write commands and data specified by the write commands from a host over a bus to a non-volatile memory system coupled to the host. Writing the data specified by the write commands from the non-volatile memory system over the bus to the host. The method further includes aggregating the data specified by the write commands in a host memory buffer maintained in memory of the host. The method further includes determining whether the data in the host memory buffer has aggregated to a threshold amount. The method further includes, in response to determining that the data has aggregated to the threshold amount, reading the data from the host memory buffer to the non-volatile memory system and writing the data to non-volatile memory in the non-volatile memory system.

Abstract: Technologies for remapping pending bit array read requests include a compute device that includes a plurality of data storage devices, a request manager, and a remap manager. The request manager is to receive a request to read pending bit array (PBA) data from a main PBA mapped to multiple sub PBAs. Each sub PBA is associated with a different one of the data storage devices. The request includes attribute data indicative of an address in the main PBA from which to read the PBA data. The remap manager is to determine one or more bit addresses from the attribute data, compare the one or more bit addresses to addresses of the sub PBAs in the main PBA to determine a set of the sub PBAs to be read, and map the one or more bit addresses to the determined set of sub PBAs to be read.