Patents Examined by Mano Padmanabhan
  • Patent number: 10509735
    Abstract: According to one embodiment, a data storage apparatus includes a controller with a data protection function. The controller manages first and second personal identification data. The first personal identification data only includes authority to request inactivation of the data protection function. The second personal identification data includes authority to request inactivation of the data protection function and activation of the data protection function. The controller permits setting of the first personal identification data, when the second personal identification data is used for successful authentication and the first personal identification data is an initial value, or when the data protection function is in an inactive state.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 17, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Isozaki, Koichi Nagai
  • Patent number: 10509599
    Abstract: A memory system having a stack memory, a set of media. and a controller. The controller divides the stack memory into a plurality of stacks, measures usages of the stacks in a period of time of operating on the set of media, and adjusts partitioning of the stack memory into the plurality of stacks according to the measured usages.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 17, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Alex Frolikov
  • Patent number: 10503641
    Abstract: A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. The cache coherence bridge protocol may be used to facilitate interoperability between host processors and processor-in-memory devices designed by different vendors and both the host processors and processor-in-memory devices may implement coherence techniques among computing units within each processor. The cache coherence bridge protocol may support different granularity of cache coherence permissions than those used by cache coherence protocols of a host processor and/or a processor-in-memory.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: December 10, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael W. Boyer, Nuwan Jayasena
  • Patent number: 10503607
    Abstract: A method and an apparatus for generating a virtual machine snapshot, where the method includes suspending a virtual machine at a first moment according to a received snapshot command, starting to perform a storage operation on a memory page in memory of the virtual machine and a contamination interception operation on the memory page in the memory, storing a device status, which is at the first moment, of the virtual machine to a snapshot file, and restoring the virtual machine from a suspended state to a running state after the device status is stored.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 10, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Hailiang Zhang
  • Patent number: 10496277
    Abstract: There are disclosed herein techniques for use in acquiring data storage metrics. The techniques comprise monitoring an I/O operation relating to data storage. The techniques also comprise producing a metric value in connection with the I/O operation. The techniques also comprise determining a current metric value associated with a memory location in an operating system kernel. The techniques also comprise performing a computation to generate a new metric value. The computation is based on the metric value and the current metric value. The techniques further comprise storing the new metric value in the memory location in the operating system kernel.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: December 3, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Wayne E. Garrett, Jr., Joseph J. Burbage, Jr.
  • Patent number: 10496464
    Abstract: A computer-implemented method, computer program product, and computing system for detecting the availability of status-related data within an FRU. The status-related data is written to persistent memory within the FRU.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: December 3, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Joseph P. King, Phil Roux, Mingxiang Xu
  • Patent number: 10489073
    Abstract: Techniques are provided for multi-tier write allocation. A storage system may store data within a multi-tier storage environment comprising a first storage tier (e.g., storage devices maintained by the storage system), a second storage tier (e.g., a remote object store provided by a third party storage provider), and/or other storage tiers. A determination is made that data (e.g., data of a write request received by the storage system) is to be stored within the second storage tier. The data is stored into a staging area of the first storage tier. A second storage tier location identifier, for referencing the data according to a format utilized by the second storage tier, is assigned to the data and provided to a file system hosting the data. The data is then destaged from the staging area into the second storage tier, such as within an object stored within the remote object store.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: November 26, 2019
    Assignee: NetApp Inc.
    Inventors: Ganga Bhavani Kondapalli, Kevin Daniel Varghese, Ananthan Subramanian, Cheryl Marie Thompson, Anil Paul Thoppil
  • Patent number: 10489088
    Abstract: A storage device includes a nonvolatile semiconductor memory module, and a host interface for connection to a host that is external to the storage device. The host interface includes a first interface circuit conforming to Serial Peripheral Interface (SPI) and a second interface circuit conforming to an interface standard different from SPI. Output terminals of the first interface circuit are connected to input terminals of the second interface circuit, and output terminals of the second interface circuit are connected to input terminals of the nonvolatile semiconductor memory module.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: November 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shunsuke Kodera, Yoshio Furuyama
  • Patent number: 10482008
    Abstract: In one example, reclaiming obsolete regions includes a memory organized in aligned memory blocks and storing valid variables in valid regions and obsolete variables in the obsolete regions. A memory includes a buffer region to cache the memory. A controller can search the buffer region for the obsolete regions and pair with respective valid regions and determine if start addresses of the obsolete regions are memory aligned and if not aligned, to write a small portion content of a first valid region to the start address of the aligned memory block, and to write any remaining respective valid region beginning at the start address of the aligned memory block and in multiples of the aligned memory block. Upon completion of a writing, moved respective valid regions begin at the starting address of the obsolete regions and new obsolete regions begin at end addresses of the moved respective valid regions.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: November 19, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Terry Ping-Chung Lee, XinLai Yu, Yi Liu
  • Patent number: 10474582
    Abstract: NAND flash storage devices and methods are provided that use a non-NAND cache to store write data until a substantially complete storage unit is available. An exemplary solid state storage device comprises a NAND flash memory device; a non-NAND cache; and a controller configured to obtain write data from a remote host for storage in the NAND flash memory device; store the write data in the non-NAND cache; and transfer the write data from the non-NAND cache to the NAND flash memory device when a predefined storage criterion is satisfied. The predefined storage criterion comprises, for example, a storage unit of the write data stored in the non-NAND cache, where the storage unit comprises a block of data erased in a single garbage collection cycle. The predefined storage criterion is optionally established to reduce open block degradation in NAND flash memory devices.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: November 12, 2019
    Assignee: Seagate Technology LLC
    Inventor: Dana L. Simonson
  • Patent number: 10467141
    Abstract: Systems and methods for improved process caching through iterative feedback are disclosed. In embodiments, a computer implemented method comprises retrieving updated metadata of a process to be executed, wherein the updated metadata includes information regarding cache misses from a prior execution of the process; automatically modifying a setting of a data stream control register based on the updated metadata; automatically setting a hint at a data cache block touch module; performing an initial execution of the process after the steps of retrieving the updated metadata, automatically modifying the setting of the data stream control register, and automatically setting the hint at the data cache block touch module; and modifying the updated metadata of the process after the execution of the process based on cache miss statistical data gathered during the execution of the process, to produce newly updated metadata.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mauro Sergio Martins Rodrigues, Rafael Camarda Silva Folco, Daniel Battaiola Kreling, Breno H. Leitao
  • Patent number: 10459659
    Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Muthukumar P. Swaminathan, Kunal A. Khochare
  • Patent number: 10452557
    Abstract: The processor provides a host computer with a logical volume based on a physical storage device. Based on a command from the host computer, the control device writes, into a memory, address information that associates a logical address in the logical volume with a device address in the physical storage device. The control device receives a command from the host computer and if it is determined that the command is a read command, identifies a first logical address designated by the command and determines whether or not the first logical address is included in the address information. If the first address is included in the address information, the control device specifies a first device address corresponding to the first logical address, reads read data stored in an area indicated by the first device address, and transmits the read data to the host computer.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: October 22, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Hirotoshi Akaike, Norio Shimozono, Kazushi Nakagawa
  • Patent number: 10445534
    Abstract: A storage device wiping system and method that is activated from a remote server or other site when a computer is reported lost or stolen. The wipe technique selectively wipes all data files and free space before beginning to wipe the entire storage device. This causes any personal data files, photos, videos, and the like to be wiped first. Once the wiping process starts, it will continue until complete. The process starts or continues whenever the computer is booted. Only when all personal and sensitive data is wiped, will the system then change the encryption key (if there is one) and begin wiping the entire storage device.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 15, 2019
    Assignee: Whitecanyon Software, Inc.
    Inventors: Donald E. Griffes, Daniel S. Pedigo, Tuvia Barak
  • Patent number: 10445004
    Abstract: A storage server includes a first controller, a second controller and physical drives. The first controller receives a request to store data in a virtual block address (VBA) of a virtual drive, determines a physical block address (PBA) of a physical drive on which to store the data, and sends to the physical drive a command to store the data at the PBA. The first controller generates a first metadata update for a first metadata table associated with the virtual drive, wherein the first metadata update indicates a mapping of the VBA to the PBA. The first controller generates a second metadata update for a second metadata table that identifies statuses of PBAs, wherein the second metadata update indicates that the PBA is valid. The first controller writes an entry to a cache in a memory, the entry comprising the first metadata update and the second metadata update.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 15, 2019
    Assignee: Pavilion Data Systems, Inc.
    Inventors: Suhas Dantkale, Venkeepuram R. Satish, Raghuraman Govindasamy
  • Patent number: 10437500
    Abstract: An example system for committing metadata to a non-volatile storage device may include a controller that includes determines a count of metadata that has been altered after being committed to the non-volatile storage device. Based on the count being above a first threshold, the controller may prevent alterations to the metadata. Based on the count being above a second threshold, the controller may commit the altered metadata to the non-volatile metadata.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 8, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Derek A. Sherlock
  • Patent number: 10437513
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 8, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Yu Cai, Yunxiang Wu, Ning Chen, Erich F. Haratsch, Zhengang Chen
  • Patent number: 10438023
    Abstract: The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: October 8, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 10423342
    Abstract: Scaling events may be detected for hosting hierarchical data structures. Scaling events may be detected to modify the capacity of a data store for hierarchical data structures to handle changing write workloads, read workloads, or storage capacity. Hierarchical data structures may be moved from one group of storage hosts to another group of storage hosts according to a filtered snapshot that includes the hierarchical data structures to be moved that is provided to the destination storage hosts. Changes made to the hierarchical data structures made at the source storage hosts during the move can be applied to the filtered snapshot so that the hierarchical data structures may be made available at the destination storage hosts inclusive of the changes.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: September 24, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mahendra Manshi Chheda, Srikanth Mandadi, Alazel Acheson, Christopher Ryan Baker, Matthew William Berry, Jr.
  • Patent number: 10423361
    Abstract: A system includes reception of a request from a first application to create a virtual open-channel solid state drive associated with a first bandwidth and first capacity, association, in response to the request, of block addresses of a virtual address space of the first application with block addresses of one or more blocks of a first one of a first plurality of channels of a first open-channel solid state drive and with block addresses of one or more blocks of a second one of a second plurality of channels of a second open-channel solid state drive, reception, from the first application, of a first I/O call associated with one or more block addresses of the virtual address space, determination of block addresses of one or more blocks of the first one of the first plurality of channels which are associated with the one or more block addresses of the virtual address space, and execution of the first I/O call on the determined block addresses of one or more blocks of the first one of the first plurality of chan
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 24, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Anirudh Badam, Badriddine Khessib, Laura Marie Caulfield, Mihail Gavril Tarta, Robin Andrew Alexander, Xiaozhong Xing, Zhe Tan, Jian Xu