Abstract: In one aspect, runtime feature overhead minimization is provided for a storage system. An aspect includes providing a system table having features available to the system and a field indicating whether a feature is enabled. An aspect also includes providing a configuration table for data modules in the system that includes features available to storage units managed by the data modules and a field that indicates whether a feature is enabled for a storage unit. Upon receiving a request that includes a selected storage unit, the data modules access the system table. For each feature in the system table, the data modules determine whether the feature is set to enabled via the corresponding flag field. Upon determining the feature is set to disabled via the corresponding flag field in the system table, performing an operation identified in the request without accessing the configuration table.

Abstract: A method for implementing a shared memory buffer includes at an apparatus comprising a processor and a physical memory, running a host environment with a host virtual memory. The method further includes running a guest environment with a guest virtual memory, performing, by the host environment, an allocation of a frame buffer in the physical memory, and mapping the allocated frame buffer into the host virtual memory. Additionally, the method includes passing a handle of the allocated frame buffer to the guest environment and performing a mapping of the allocated frame buffer into the guest virtual memory, the mapping based on the handle of the allocated frame buffer.

Abstract: Apparatus and method for managing data in a multi-device data storage system. In some embodiments, a plurality of data storage devices are provided, each data storage device having a local driver circuit adapted to transfer data with a local memory module. A main driver circuit external to the plurality of data storage devices is configured to stream frequency modulated write data via parallel data transfer paths to the respective local driver circuits for concurrent transfer of the frequency modulated write data to the respective local memory modules.

Abstract: A processor core executes a first instruction indicating a first coherence state update policy that biases the cache memory to retain write authority, thereafter executes a second instruction indicating a second coherence state update policy that biases the cache memory to transfer write authority, and executes a store instruction following the first instruction in program order to generate a store request. A cache memory stores the cache line in association with a coherence state field set to a first modified coherence state. In response to the store request, the cache memory updates data of the cache line. If the store instruction is executed prior to the second instruction, the cache memory refrains from updating the coherence state field, but if the store instruction is executed after the second instruction, the cache memory updates the coherence state field from the first modified coherence state to a second modified coherence state.

Abstract: Techniques are disclosed herein for providing accelerated recovery techniques of a memory device. Such techniques can allow for recovery of the memory device, such as, but not limited to, a flash memory device, following an unexpected reset event.

Abstract: An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.

Abstract: A method is used in managing deduplication characteristics in a storage system. Deduplication entries stored in a deduplication cache are categorized into a set of deduplication groups based on a data deduplication probability associated with the deduplication entries. A machine learning system is used to dynamically adjust deduplication characteristics associated with the set of deduplication groups based on an I/O workload associated with the storage system.

Abstract: An exemplary data refresh method disclosed herein reading data into volatile memory from a first storage region using a read element controlled by a first actuator assembly and writing the data from the volatile memory to a second storage region using a write element controlled by a second actuator assembly, where the first actuator assembly and the second actuator assembly are configured to receive data from control circuitry via independent read/write communication channels.

Abstract: Recovery support techniques for storage virtualization environments are described. In one embodiment, for example, a method may be performed that comprises defining, by processing circuitry, a storage container comprising one or more logical storage volumes of a logical storage array of a storage system, associating the storage container with a virtual volume (vvol) datastore, identifying metadata for a vvol of the vvol datastore, and writing the metadata for the vvol to the storage system. Other embodiments are described and claimed.

Abstract: An aspect of the present disclosure provides for managing content items in a storage system. In an embodiment, a trash command is received from a user, where the trash command specifies an expression of a set of attribute conditions connected by logical operators. A set of content items having attributes matching said expression are selected, where the set of content items are stored in corresponding logical locations on the storage system prior to receiving the trash command. The selected set of content items are moved from respective logical locations on the storage system to a set of trash folders, wherein selecting and moving the set of content items are performed in response to receiving the trash command specifying the expression.

Abstract: A data storage system stores information indicating a determined sequence for performing operations on a data store. A lock is acquired on a portion of the data store. It is determined that performing the operations comprises performing at least one additional operation on the data store. Uncommitted changes implied by the operations are stored in a transaction buffer according to the determined sequence. Changes implied by the additional operation are determined based on a reentrant call to a data store interface. The logged sequence of changes is applied to the data store and the lock is released.

Abstract: A system for writing to a cache line, the system including: at least one processor; and at least one memory having stored thereon instructions that, when executed by the at least one processor, controls the at least one processor to: pre-emptively invalidate a cache line at a reader device; receive, from the reader device, a read request for the invalidated cache line; delay a response to the read request; and after the delay, output for transmission a response to the read request to the reader device.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for seed scrambling. An apparatus includes a memory element. An apparatus includes a scrambler component. A scrambler component includes an input circuit that receives a random seed. A scrambler component includes a matrix circuit that generates a new seed based on a matrix operation performed on a seed. A scrambler component includes a rotation circuit that forms a shifted seed. A shifted seed is formed by shifting a new seed based on a seed.

Abstract: To reduce overhead for cache coherence for shared cache in multi-processor systems, adaptive granularity allows tracking shared data at a coarse granularity and unshared data at fine granularity. Processes for adaptive granularity select how large of an entry is required to track the coherence of a block based on its state. Shared blocks are tracked in coarse-grained region entries that include a sharer tracking bit vector and a bit vector that indicates which blocks are likely to be present in the system, but do not identify the owner of the block. Modified/unshared data is tracked in fine-grained entries that permit ownership tracking and exact location and invalidation of cache. Large caches where the majority of blocks are shared and not modified create less overhead by being tracked in the less costly coarse-grained region entries.

Abstract: A logic-executing ring buffer (LERB) is a ring buffer with integrated logic. A LERB includes a series of logical ring stages and corresponding ring entries mapped to each other using an indirection table. A LERB can include control logic and stage functions that execute in association with each ring stage. The LERB advances by updating the indirection table (e.g., to map an associated ring entry with a subsequent ring stage, optionally based on pinning logic) and/or by passing data from one ring stage to the next. As such, ring stages can store transient data that gets passed between ring stages, ring entries store persistent data that does not move, and mappings are updated by LERB control logic and/or stage functions. As such, a LERB is a flexible data structure that provides expanded functionality and improved memory management for many applications.

Abstract: A system and method of emulated input-output memory management units includes a management software associating a first device with a first input-output memory management unit having a first security designation, and associating a second device with a second input-output memory management unit having a second security designation different from the first security designation. A hypervisor constructs a table that describes associations between the plurality of devices and the plurality of input-output memory management units. The hypervisor provides the table to a guest virtual machine having a plurality of guest addresses including a first guest address and a second guest address. The first device accesses the first guest address through the first input-output memory management unit and the second device accesses the second guest address through the second input-output memory management unit.

Abstract: The present application relates to a storage device operation control method, a storage device, and a management node. The method includes: receiving at least one request sent by at least one management node; and when one of the at least one request is a permission application request, determining, according to a current permission status, whether to assign operation permission to a management node that sends the permission application request; or when one of the at least one request is an operation request, determining, according to a current permission status, whether a management node that sends the operation request has operation permission, and performing an operation according to the operation request when the management node that sends the operation request has the operation permission. This avoids a conflict caused by simultaneously performing an operation on a storage device by multiple management nodes, and prevents successive serial operations from being interrupted.

Abstract: A data storage device and a method for operating the data storage device are disclosed. The data storage device may include an interface receiving a command and data from a host, a cache temporarily storing the received data, a memory non-temporarily storing the data stored in the cache, and a controller controlling the memory and the cache based on the command received from the host. The command may include charge rate of a battery supplying a power to the data storage device. The controller may determine whether or not the data storage device is an idle state, and determine an active operation mode of the data storage device based on the charge rate of the battery, when the data storage device is the idle state.

Abstract: A storage device may utilize a host memory buffer for re-ordering commands in a submission queue. Out of order commands in a submission queue that uses host virtual buffers that are not the same size may be difficult to search. Accordingly, commands in a submission queue may be correctly ordered in a host memory buffer before being put into the host virtual buffers. When the commands are in order, the search operation for specific data is improved.

Abstract: Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.