Abstract: According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of first conductive layers, a memory columnar body, a first semiconductor layer, a second semiconductor layer and a contact. The plurality of first conductive layers are stacked upwardly of the substrate. The memory columnar body extends in a first direction intersecting an upper surface of the substrate and a side surface of the memory columnar body is covered by the first conductive layers. The first semiconductor layer is connected to a lower end of the memory columnar body and extends in a second direction intersecting the first direction. The second conductive layer is provided between the first semiconductor layer and the first conductive layers. The second conductive layer is connected to the memory columnar body and extending in the second direction. The contact is connected to the second conductive layer and extends in the first direction.

Abstract: In various embodiments, image sensors and methods of making images sensors are disclosed. In an embodiment, an image sensor includes a first pixel region having a pixel electrode, an optically sensitive material of a first thickness, and a counterelectrode. The images sensor also includes a second pixel region comprising a pixel electrode, an optically sensitive material of a second thickness, and a counterelectrode. The first pixel region is configured to detect light in a first spectral band and the second pixel region is configured to detect light in a second spectral band. The first and second spectral bands include an overlapping spectral range. The second spectral band also includes a spectral range that is substantially undetectable by the first pixel region. Other image sensors and methods of making images sensors are also disclosed.

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings.

Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.

Abstract: The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack.

Abstract: In order to realize a silicon PUF of lower power consumption, a semiconductor device includes first and second MIS transistors of the same conductive type in off-state coupled in series, as a PUF element. The PUF element outputs a signal of high level or low level depending on the potential of a connection node of the first and the second MIS transistors. Preferably, the MIS transistors are fin-type FETs.

Abstract: A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.

Abstract: A method of producing wettable fillets in electronic packages. A matrix of unsingulated lead frames is provided, each including a plurality of lead elements and a chip pad. Chips are attached to the chip pads and terminals on the chips are electrically connected to lead portions of the lead elements. The top portion of the package is encapsulated. Masking is applied to the bottom surface of the lead elements and the chip pads, but at least one of the lead elements has a portion of its surfaced remaining exposed. The exposed lead element surface is etched to create a fillet. The fillets, lead elements and bottom surface of the chip pads are plated, and the packages then singulated, producing packages with wettable flanks.

Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. Providing the pinned and/or free layer(s) includes providing a magnetic layer including a glass-promoting component, providing a sacrificial oxide layer on the magnetic layer, providing a sacrificial layer on the sacrificial oxide layer and performing at least one anneal of the magnetic layer, the sacrificial oxide layer and the sacrificial layer at anneal temperature(s) greater than 300 degrees Celsius and not exceeding 475 degrees Celsius. The magnetic layer is amorphous as-deposited but is at least partially crystallized after the anneal(s). The sacrificial layer includes a sink for the glass-promoting component. The sacrificial layer and the sacrificial oxide layer are removed after the anneal(s).

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.

Abstract: Integrated circuit (IC) packages with an inter-die thermal spreader are disclosed. A disclosed IC package includes a plurality of stacked dies disposed on a package substrate. A heat spreader is disposed on a top die of the plurality of stacked dies. The IC package further includes a thermal spreader layer disposed adjacent to at least one die of the plurality of stacked dies. The thermal spreader layer may extend out of a periphery of the plurality of stacked dies and may be attached to the heat spreader through a support member.

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.

Abstract: Disclosed is an avalanche photodiode using a silicon nanowire, including a first silicon nanowire formed of silicon (Si), a first conductive region formed by doping one surface of the first silicon nanowire with a first dopant, and a second conductive region formed by doping one surface of the first silicon nanowire with a second dopant having a conductive type different from that of the first dopant so as to be arranged continuously in a longitudinal direction from the first conductive region, wherein, when the magnitude of a reverse voltage applied to both ends of the first silicon nanowire is equal to or greater than a preset breakdown voltage, avalanche multiplication of inner current occurs due to the incidence of light from the outside.

Abstract: Disclosed is a thin-film transistor. The thin-film transistor includes: a substrate; a first gate, a first gate insulation layer, a semiconductor layer, an etching stop layer, and the second gate stacked on a surface of the substrate, in which the semiconductor layer has a thickness of 200 nm-2000 nm; the etching stop layer includes a first via and a second via formed therein; and the first via and the second via are arranged to each correspond to the semiconductor layer; and a source and a drain respectively extending through the first via and the second via to connect to the semiconductor layer. The thin-film transistor has an increased ON-state current and switching speed.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.

Abstract: A pressure sensor comprises a deformable membrane deflecting in response to pressure applied, a first stationary electrode, and a second electrode coupled to the deformable membrane, for determining a change in a capacitance between the first and the second electrode in response to the pressure applied. At least one of the first and the second electrode comprises a getter material for collecting gas molecules.

Abstract: A method for generating a non-volatile memory device may comprise: applying plasma for a preset time period to an exposed surface of a channel of a field effect transistor such that a plurality of charge-trapping sites are formed at the channel. The channel is comprised of a multi-layer structure of atomically thin two-dimensional sheets.

Abstract: A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.