Abstract: An embedded component substrate includes: a core layer; a first electrode provided on a top surface of the core layer with a first insulating layer therebetween; and a second electrode provided on a bottom surface of the core layer with a second insulating layer therebetween, wherein a cavity is formed in the embedded component substrate from a top surface thereof to expose the second insulating layer at a bottom of the cavity, wherein a placement region is defined on the bottom of the cavity, for accommodating an electronic component; and wherein the embedded component substrate further includes a pad electrode on a portion of the second insulating layer, exposed by the cavity, surrounding the placement region located on the bottom of the cavity, the pad electrode vertically protruding from a top surface of the exposed second insulating layer upwardly and being configured to electrically connect to the electronic component.

Abstract: A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Abstract: A method of fabricating a semiconductor device may form a nitride semiconductor layer on a substrate, form a first insulator layer on the nitride semiconductor layer by steam oxidation of ALD, form a second insulator layer on the first insulator layer by oxygen plasma oxidation of ALD, form a gate electrode on the second insulator layer, and form a source and drain electrodes on the nitride semiconductor layer. The nitride semiconductor layer may include a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer.

Abstract: A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.

Abstract: The present disclosure provides an inductor structure. The inductor structure, comprising a first surface, a second surface intersecting with the first surface, a first conductive pattern and a second conductive pattern. The first conductive pattern is formed on the first surface. The second conductive pattern is formed on the second surface. The first conductive pattern is connected with the second conductive pattern.

Abstract: A method of fabricating LEDs from a wafer comprising a substrate and epitaxial layers and having a substrate side and a epitaxial side, said method comprising: (a) applying a laser beam across at least one of said substrate side or said epitaxial side of said wafer to define at least one laser-scribed recess having a laser-machined surface; and (b) singulating said wafer along said laser-scribed recess to form singulated LEDs, said singulated LEDs having a top surface, a bottom surface, and a plurality of sidewalls, at least one of said sidewalls comprising at least a first portion comprising at least a portion of said laser-machined surface.

Abstract: A vertical semiconductor device comprises a substrate having a front surface and a back surface, an active area (AA) located in the substrate, having a drift region doped with a first dopant type, an edge termination region (ER) laterally surrounding the active area (AA), a channelstopper terminal provided at the front surface and located in the edge termination region (ER), and a first suppression trench located on a side of the channelstopper terminal towards the active region (AA), and provided adjacent to the channelstopper terminal. Further, a production method for such a semiconductor device is provided.

Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer comprising cobalt, iron, and boron formed adjacent to the insulating tunnel junction layer; a second magnetic reference layer comprising cobalt separated from the first magnetic reference layer by a molybdenum layer; an iridium layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the iridium layer. The magnetic free layer structure includes a first and a second magnetic free layers with a perpendicular enhancement layer interposed therebetween. The first and second magnetic reference layers have a first invariable magnetization direction perpendicular to layer planes thereof.

Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first conductive plug and a second conductive plug over the semiconductor substrate and adjacent to each other. The semiconductor device structure includes a first conductive via structure and a second conductive via structure over the semiconductor substrate and adjacent to each other. A first distance between the first conductive plug and the second conductive plug is less than a second distance between the first conductive via structure and the second conductive via structure. A first height of the first conductive plug is greater than a second height of the first conductive via structure.

Abstract: A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is fondled from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

Abstract: A single-poly nonvolatile memory cell includes a coupling capacitor, a cell transistor and a selection transistor. The cell transistor has a floating gate, a first source, and a first drain. The floating gate is coupled to an array control gate/source line through the coupling capacitor. The first source is coupled to the array control gate/source line. The selection transistor has a selection gate, a second source, and a second drain. The selection gate is coupled to a word line. The second source is coupled to the first drain. The second drain is coupled to a bit line.

Abstract: A photoelectric conversion device includes: a first optical filter that has a first pattern periodically having a plurality of structures and is formed of a conductive material film disposed on a first photoelectric conversion element with an insulating film therebetween; and a first optical filter that has a second pattern periodically having a plurality of structures and is formed of a conductive material film disposed on a second photoelectric conversion element with the insulating film therebetween. The interval between the first pattern and the second pattern that are adjacent to each other is longer than a period of the structures in the first pattern and a period of the structures in the second pattern.

Abstract: The invention relates to a switching device for switching radio frequency signals. The switching devices comprises at least a first field effect transistor that comprises a first source node, a first gate node and a first drain node, wherein the first gate node is arranged between a first drain region and a first source region on a semiconductor substrate. The switching device comprises at least a second field effect transistor that comprises a second source node, a second gate node and a second drain node, wherein the second gate node is arranged between a second drain region and a second source region on the same semiconductor substrate. The first source region of the first transistor is directly connected to the second drain region of the second transistor to build a common node of the switching device. An input node and an output node of the switching device are directly connected to the common node.

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

Abstract: The invention relates to a mold for encapsulating electronic components mounted on a carrier, with at least two mold parts which are displaceable relative to each other for engaging with a mold cavity round electronic components, and at least one feed for encapsulating material recessed into the mold parts and connecting to the mold cavity. The invention also relates to a carrier with encapsulated electronic components. The invention further relates to a method for encapsulating electronic components and to the thus manufactured encapsulated separated components. The carrier is provided with a plurality of recessed through-openings located at a distance from the electronic components and an encapsulation arranged round the electronic components, wherein through-openings are recessed into the encapsulating material and wherein some of the through-openings recessed into the carrier coincide at least partially with the through-openings recessed into the encapsulating material.

Abstract: The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.