Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.

Abstract: Methodologies and a device for reducing capacitance and improving profile control are provided. Embodiments include forming metal vias in a first dielectric layer; forming a graded interlayer dielectric over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon film over the metal layer.

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

Abstract: A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.

Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; an oxide layer formed adjacent to the magnetic free layer structure; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure opposite the oxide layer; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a perpendicular enhancement layer; an antiferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the antiferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.

Abstract: Systems and methods for providing a solid state image sensor (30) are provided. More particularly, an image sensor (30) that suppresses color mixing is provided. Moreover, embodiments of the present disclosure provide for the creation of light blocking features (32) that avoid the creation of stress concentrations. More particularly, embodiments of the present disclosure provide for the creation of light blocking structures (32) using trenches formed in a substrate (44) that are arranged such that no two trenches intersect one another.

Abstract: A method for manufacturing metal structures for the electrical connection of components comprises the following steps: depositing an auxiliary layer on a substrate; structuring the auxiliary layer in a manner such that the substrate is exposed at least one environment which is envisaged for the metal structures; depositing a galvanic starting layer on the structured auxiliary layer; depositing a lithography layer on the galvanic starting layer and structuring the lithography layer in a manner such that the galvanic starting layer is exposed at least one location envisaged for the metal structure; galvanically depositing the at least one metal structure at the at least one exposed location; removing the structured auxiliary layer. An electronic component is also described.

Abstract: A process flow for forming a magnetic tunnel junction (MTJ) cell that is self-aligned to an underlying bottom electrode (BE) is disclosed. The BE is comprised of a lower BE layer having a first width (w1), and an upper (second) BE layer with a second width (w2) where w2>w1. Preferably, the BE has a T shape. A stack of MTJ layers including an uppermost hard mask is deposited on the BE and has width w2 because of a self-aligned deposition process. A dummy MTJ stack is also formed around the first BE layer. An ion beam etch where ions are at an incident angle <90° with respect to the substrate is used to remove extraneous material on the sidewall. Thereafter, an encapsulation layer is deposited to insulate the MTJ cell, and to fill a gap between the first BE layer and dummy MTJ stack.

Abstract: Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the method, sacrificial gates are removed from partially completed transistors, creating gate openings that expose sections of semiconductor fins between source/drain regions. Prior to forming replacement metal gates in the gate openings, additional process steps are performed so that, in the resulting IC structure, some transistors have different channel region heights and, thereby different effective channel widths, than others. These steps can include forming isolation regions in the bottoms of some gate openings. Additionally or alternatively, these steps can include filling some gate openings with a sacrificial material, recessing the sacrificial material to expose fin tops within those gate openings, either recessing the fin tops or forming isolation regions in the fin tops, and removing the sacrificial material.

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

Abstract: A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance.

Abstract: A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the semiconductor substrate, and forming second well regions and a third well region in the first well region, wherein the second well regions are isolated from the third well region by the isolation structures, and two of the adjacent second well regions have a first distance between them. The method also includes performing a rapid thermal annealing process to shorten the first distance to a second distance. The method further includes forming first barrier metal layers on the first well region and covering the second well regions, forming a second barrier metal layer on the first well region and covering the third well region, forming first electrodes on the first barrier metal layers, and forming a second electrode on the second barrier metal layer.

Abstract: A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that includes one type of semiconductor (e.g. germanium) and an upper portion of another type of semiconductor (e.g. indium arsenide. The lower portion of the column provides a channel region for a transistor of one type, while the upper column provides a channel region for a transistor of another type. This provides a complementary pair that occupies a minimum of integrated circuit surface area. The complementary transistors can be utilized in a variety of circuit configurations. Described are complementary transistors where the lower transistor is p-type and the upper transistor is n-type.

Abstract: First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conveying at least one signal between the optical components on the first and second integrated devices.

Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to oxidize the first sidewall surfaces of the fins to form a first oxide layer, and to oxidize the second sidewall surfaces of the fins to form a second oxide layer, a thickness of the first oxide layer being different from a thickness of the second oxide layer, and un-oxidized portions of the fins between the first oxide layer and the second oxide layer being configured as channel layers; removing the second oxide layer and a partial thickness of the first oxide layer; and forming a gate structure crossing over the channel layers over the semiconductor substrate.