Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of a first band-gap material, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the first band-gap material directly adjoining the drift region and the metallization, and an anode region of a second band-gap material having a lower band-gap than the first band-gap material. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate structure, multiple fins having a germanium layer, a dummy gate structure including sequentially a hardmask, a dummy gate, a dummy gate insulating material on the germanium layer, and spacers on opposite sides of the dummy gate structure and on a portion of the germanium layer. The method also includes forming an interlayer dielectric layer on the substrate structure covering the dummy gate structure, planarizing the interlayer dielectric layer to expose a surface of the dummy gate, removing the dummy gate and the dummy gate insulating material to expose a surface of the germanium layer, performing a silane impregnation process on the exposed surface of the germanium layer to introduce silicon to the germanium layer, and performing an oxidation process on the germanium layer to form an oxide layer comprising silicon and germanium.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.

Abstract: A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.

Abstract: A method for fabricating a transistor is provided. The method includes providing a semiconductor substrate; and forming at least a nanowire suspending in the semiconductor substrate. The method also includes forming a channel layer surrounding the nanowire; and forming a contact layer surrounding the channel layer. Further, the method includes forming a trench exposing the channel layer and surrounding the channel layer in the contact layer; and forming a potential barrier layer on the bottom of the trench and surrounding the channel layer. Further, the method also includes forming a gate structure surrounding the potential barrier layer and covering portions of the contact layer; and forming a source and a drain region on the contact layer at two sides of the gate structure, respectively.

Abstract: A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.

Abstract: Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.

Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.

Abstract: A method of making a semiconductor device includes doping a first portion of an interlayer dielectric (ILD) with an oxygen-containing material, wherein the ILD is over a substrate. The method further includes doping a second portion of the ILD with a large species material. The second portion includes an area of the ILD below the first portion, and the second portion is separated from the substrate. The method further includes annealing the ILD.

Abstract: An image sensor includes a semiconductor substrate integrated with at least one first photo-sensing device configured to sense light in a blue wavelength region and at least one second photo-sensing device configured to sense light in a red wavelength region, a color filter layer on the semiconductor substrate and including a blue color filter configured to selectively absorb light in a blue wavelength region and a red color filter configured to selectively absorb light in a red wavelength region, and a third photo-sensing device on the color filter layer and including a pair of electrodes facing each other, and a photoactive layer between the pair of electrodes and configured to selectively absorb light in a green wavelength region.

Abstract: A semiconductor device may include a first conductive pattern disposed in a first interlayer insulating film, a second conductive pattern disposed in a second interlayer insulating film positioned on the first interlayer insulating film, a through electrode partially penetrating through the first interlayer insulating film and the second interlayer insulating film. The through electrode electrically connects the first conductive pattern and the second conductive pattern. The device further includes a first pattern completely surrounding side surfaces of the through electrode, and a second pattern between the first pattern and the through electrode. The second pattern is separated from the first pattern and the through electrode. The device includes a third pattern connecting the first pattern and the second pattern.

Abstract: Magnetic memory devices include an array of magnetic memory cells including magnetic tunnel junction regions. The array of magnetic memory cells includes access lines extending in a column direction and data/sense lines extending in a row direction transverse to the column direction. A common source plate electrically couples magnetic memory cells of the array in both the column direction and the row direction. Electronic systems include such a magnetic memory device operably coupled to a processor, to which at least one input device and at least one output device is operably coupled. Methods of fabricating magnetic memory devices include forming such an array of magnetic memory cells including a common source plate.

Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: After providing a Group IV semiconductor nanowire on a substrate, a sacrificial material portion is formed on sidewalls of a bottom portion of the Group IV semiconductor nanowire. A sacrificial gate layer is then formed over the sacrificial material portion to laterally surround a middle portion of the Group IV semiconductor nanowire, followed by forming a sacrificial spacer on sidewalls of a remaining top portion of the Group IV semiconductor nanowire. After replacing the Group IV semiconductor nanowire with a Group III-V compound semiconductor nanowire, the sacrificial material portion, sacrificial spacer and sacrificial gate layer are replaced by a first epitaxial semiconductor region which serves as a bottom source/drain region, a second epitaxial semiconductor region which serves as a top source/drain region, and a functional gate structure, respectively.

Abstract: Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.

Abstract: A semiconductor device includes: a semiconductor element; a frame which has a first surface, holds the semiconductor element on the first surface, and is electrically connected with the semiconductor element; and a seal which has electrical insulation properties and seals the semiconductor element and the frame, wherein a through-hole is formed in the seal, the through-hole has a hole axis which extends in a direction intersecting with the first surface, and an inner peripheral end surface of the seal exposed inside the through-hole is inclined with respect to the hole axis.

Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.