Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second zone is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second zone. The updated second XOR data is copied from the RAM1 to the RAM2.

Abstract: An apparatus comprises a processing device configured to control delivery of input-output operations from a host device to a storage system over selected ones of a plurality of paths through a network. The processing device is further configured to receive first and second data outputs corresponding to a plurality of groups of the storage system, to compute first and second pluralities of checksums for respective ones of the groups based on the first and second data outputs, and to determine for the respective ones of the groups whether given ones of the second plurality of checksums differ from given ones of the first plurality of checksums. The control of delivery of the input-output operations is based at least in part on the determination. The plurality of groups each correspond to a plurality of storage devices and the second data output is received after the first data output.

Abstract: Systems and methods are provided for storing data blocks in distributed storage. One exemplary computer-implemented method includes, in response to receipt of a data block comprising data, generating a value N for the data block, wherein the value N includes a variable integer greater than one and dividing the data block into N segments, wherein each segment includes a portion of the data. The method also includes generating a value M for the data block, wherein the value M includes a variable integer greater than or equal to one, and adding M segments of chaff to the N segments. The method then includes encrypting the N segments and the M segments of chaff and distributing the M segments and the N segments in distributed storage, wherein the N segments and the M segments of chaff are stored in multiple different storage devices included in the distributed storage.

Abstract: A storage control apparatus, includes a memory; and a processor coupled to the memory and configured to: receive management information for managing data stored in a first storage device, generate, for each processing unit of the data, restoration information for restoring the management information, add the data to the restoration information by processing the data based on the management information on a second storage device, store, in the first storage device, the added restoration information, and reconstruct the management information on the second storage device based on the added restoration information when detecting an abnormality occurrence on the receiving the management information.

Abstract: A storage device communicates with a host including a host memory. The storage device includes a semiconductor memory device and a device memory. The semiconductor memory device includes a plurality of non-volatile memory cells. The device memory stores validity information of host performance booster (HPB) sub-regions included in each of HPB regions cached in the host memory. The storage device determines to deactivate at least one HPB region among the HPB regions cached in the host memory based on the validity information included in the device memory, and transfers a message recommending to deactivate the determined HPB region to the host.

Abstract: A storage device for preventing occurrence of a read fail has a reduced overhead. The storage device includes a memory device with a plurality of memory blocks; and a memory controller for managing a fail block and a shared block as bad blocks. The fail block is determined to be a bad block among the plurality of memory blocks. The shared block is a memory block that shares a control signal for selecting the fail block in the memory device.

Abstract: A data accessing method, a memory control circuit unit, and a memory storage device are provided. The data accessing method includes the following steps. A reading command is received from a host system, in which the reading command instructs to read a first logical address, the first logical address is mapped to a first physical programming unit, and the first physical programming unit corresponds to a first physical erasing unit. A first data is generated after receiving the reading command, and the first data is written to a second physical programming unit included in the first physical erasing unit. A second data stored in the first physical programming unit is read after the first data is written, so as to respond to the reading command.

Abstract: Storage arrays in a mirror relationship use dynamic compression dictionary size adjustment and data buffer merging to more efficiently compress data associated with maintenance of consistency of a replicated storage object. A compression dictionary size selector selects a supported compression dictionary size based on the aggregate size of the updates enqueued for transmission in the data buffers, e.g., a compression dictionary size that is greater than or equal to, and as close as possible to, the aggregate size of the enqueued updates. A combiner selects enqueued updates based on the selected compression dictionary size, e.g., aggregate enqueued update size less than or equal to, and as close as possible to, the selected compression dictionary size. The selected updates are coalesced and compressed using the selected compression dictionary size.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory, a sensor measuring temperature, and a controller controlling the nonvolatile memory in accordance with the temperature measured by the sensor. The controller selects a write scheme based on the temperature measured by the sensor at a time of a write process of data with respect to the nonvolatile memory, generates management data including the write scheme with respect to the data, writes the data to the nonvolatile memory in accordance with the write scheme, obtains the write scheme with respect to the data from the management data at a time of a read process of the data, and reads the data from the nonvolatile memory in accordance with the write scheme.

Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

Abstract: A data programming method includes the following operations: assigning a first identity code to initial data according to a data type of the initial data; packing the first identity code, the initial data, and a check code to a new data packet; determining whether a first storage space in a flash memory stores a first data packet being the same as the new data packet; and if the first storage space does not store the first data packet, programming the new data packet to the first storage space in a first address sequence.

Abstract: A method and apparatus for performing data protection regarding a non-volatile memory (NVM) are provided. The method includes: obtaining a first die-dependent seed and a second die-dependent seed, where the first die-dependent seed and the second die-dependent seed correspond to a die for implementing the NVM; performing rearrangement on multiple sets of address information of an address according to the first die-dependent seed, for protecting the address carried by at least one address signal between the controller and the NVM; and performing rearrangement on multiple subsets of a set of data according to the second die-dependent seed, for protecting the set of data carried by at least one data signal between the controller and the NVM.

Abstract: A memory manager includes an internal memory and a hash function circuit. The internal memory includes a V2H (virtual address to hash function) table and an exception mapping table. The V2H table stores at least one virtual address group and a type information on a hash function mapped to the virtual address group. The exception mapping table stores at least one exception virtual address not translated into a physical address by the hash function in the virtual address group and a physical address mapped to the exception virtual address. The has function circuit checks, when a virtual address is provided from a host, type information on a hash function mapped to a virtual address group including the virtual address, by referring to the V2H table included in the internal memory. The has function translates the virtual address into a physical address by using the hash function corresponding to the type information.

Abstract: Technologies for utilizing a split memory pool include a compute sled. The compute sled includes multiple processors communicatively coupled together through a processor communication link. Each processor is to communicate with a different memory sled through a respective memory network dedicated to the corresponding processor and memory sled. The compute sled includes a compute engine to generate a memory access request to access a memory address in far memory. The far memory includes memory located on one of the memory sleds. The compute engine is also to determine, as a function of the memory address and a map of memory address ranges to the memory sleds, the memory sled on which to access the far memory, and send the memory access request to the determined memory sled to access the far memory associated with the memory address.

Abstract: A memory system may include a plurality of nonvolatile memory devices, a first operation unit configured to perform a first operation on target data stored in target nonvolatile memory devices, and one or more second operation units configured to perform second operations. The first operation unit performs the first operation by reading target data and parity data from nonvolatile memory devices not associated with second operations concurrently performed by the second operation units.

Abstract: Examples include an apparatus which accesses secure pages in a trust domain using secure lookups in first and second sets of page tables. For example, one embodiment of the processor comprises: a decoder to decode a plurality of instructions including instructions related to a trusted domain; execution circuitry to execute a first one or more of the instructions to establish a first trusted domain using a first trusted domain key, the trusted domain key to be used to encrypt memory pages within the first trusted domain; and the execution circuitry to execute a second one or more of the instructions to associate a first process address space identifier (PASID) with the first trusted domain, the first PASID to uniquely identify a first execution context associated with the first trusted domain.

Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes a read counter configured to store a block read count value of a super block and memory blocks within a non-super block as a status information in an internal memory by counting a number of times that a read operation is performed on the memory blocks; and a super block manager configured to: store a super block reclaim trigger reference and a non-super block reclaim trigger reference, which is set for the super block and the non-super block, as the status information in the internal memory, divide data stored in the memory blocks into hot data and cold data according to the block read count value, and copy the hot data in the non-super block to the super block according to the status information.

Abstract: According to certain embodiments, a memory module is operable with a memory controller of a host system. The memory module includes a module controller configurable to receive address and control signals from the memory controller, and dynamic random access memory elements configurable to communicate data signals with the memory controller in accordance with the address and control signals. The module controller has an open-drain output and is configurable to drive the open-drain output with a first signal to indicate a parity error having occurred when the memory module is being accessed for a normal memory read or write operation. The module controller is further configurable to drive the open drain output with a second signal related to one or more training sequences when the memory module performs operations associated with the one or more training sequences and not associated with any normal memory read or write operations.

Abstract: A FPGA-based intelligent storage control system is provided that includes a FLASH main controller; a FLASH command former and an address generator with a memory function, for generating level signal of cross clock domain and automatically avoiding out-of-bounds writing. A configuration data former provides for driving and controlling a configuration writing in function by a writing configuration drive signal. An automatic reading configurator provides automatic configuration reading by internal drive signal to drive. A main data and auxiliary data former provides continuous storage of main data according to ping-pong operation for unequal width RAM operation. A FLASH data reading buffer and a multi-interface external drive module are also present. The system is applicable to an unmanned underwater vehicle and underwater acoustic equipment.