Patents Examined by Mardochee Chery
  • Patent number: 11379128
    Abstract: Systems, storage devices, and methods for application-based storage device configuration settings are described. A storage device may receive a storage command and dynamically select an application set of configuration settings for processing the storage command, where the configuration settings include trim parameters for writing data units to the storage medium of the storage device.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Patent number: 11379411
    Abstract: A system and method for replicating a file system. The method includes: copying a portion of the file system from a first storage, wherein the at least a portion of the file system includes underlying data and metadata, wherein the metadata includes pointers to the underlying data and metadata defining a file system hierarchy; partitioning the copied data of the file system into a plurality of blobs, wherein the plurality of blobs includes a plurality of data blobs and a plurality of metadata blobs, wherein each data blob includes at least one portion of the underlying data; generating a plurality of filter objects based on the copied data, wherein each filter object includes a list of metadata blobs; and storing the plurality of blobs and the plurality of filter objects in a second storage.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 5, 2022
    Assignee: Vast Data Ltd.
    Inventors: Vladimir Zdornov, Asaf Levy, Asaf Weissman, Or Dahan, Hillel Costeff
  • Patent number: 11366612
    Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: June 21, 2022
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Takehiko Kurashige
  • Patent number: 11366767
    Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: June 21, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegyu Lee, Jisoo Kim, Young-Jin Park, Bo-Ram Shin
  • Patent number: 11360912
    Abstract: A method for performing adaptive locking range management, an associated data storage device and a controller thereof are provided. The method may include: receiving a security command from outside of the data storage device, wherein the security command is related to changing an old locking range into a new locking range; obtaining a start Logical Block Address (LBA) and a length value of the new locking range according to the security command; determining whether the start LBA of the new locking range is less than an end LBA of the old locking range, and determining whether an end LBA of the new locking range is greater than a start LBA of the old locking range; and in response to both determination results being true, performing data trimming on any respective non-overlapped portions of the new locking range and the old locking range.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: June 14, 2022
    Assignee: Silicon Motion, Inc.
    Inventors: Chih-Yu Lin, Hung-Ting Pan, Sung-Ling Hsu
  • Patent number: 11354056
    Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Samir Mittal, Anirban Ray, Gurpreet Anand
  • Patent number: 11354253
    Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 7, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegyu Lee, Jisoo Kim, Young-Jin Park, Bo-Ram Shin
  • Patent number: 11347606
    Abstract: Determining active membership among a set of storage systems synchronously replicating a dataset, where determining active membership includes: determining that a membership event corresponds to a change in membership to the set of storage systems synchronously replicating the dataset; applying, in dependence upon the membership event, one or more membership protocols to determine a new set of storage systems to synchronously replicate the dataset; and for one or more I/O operations directed to the dataset, applying the one or more I/O operations to the dataset synchronously replicated by the new set of storage systems.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: May 31, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Connor Brooks, Thomas Gill, David Grunwald, Ronald Karr, Aswin Karumbunathan, Naveen Neelakantam, Zoheb Shivani, Kunal Trivedi
  • Patent number: 11347424
    Abstract: Systems and methods for processing data segments are disclosed. In one embodiment, such functionality includes buffering data received from a node (where the data is stored in a buffer as buffered data, an offset value is associated with the data, and a segment size is associated with the buffer), and determining whether the offset value is an integer multiple of the segment size. In response to determination that the offset value is an integer multiple of the segment size, processing the data in the buffer as a segment. Such functionality also includes determining whether the segment is a duplicate of data stored in a deduplicated data store and, in response to a determination that the segment is not a duplicate of data stored in the deduplicated data store, storing the segment in the deduplicated data store.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 31, 2022
    Assignee: VERITAS TECHNOLOGIES LLC
    Inventors: Xianbo Zhang, Yong Yang
  • Patent number: 11340833
    Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shanky Kumar Jain, Dmitri A. Yudanov
  • Patent number: 11327885
    Abstract: There are provided a controller and a memory system having the controller.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: May 10, 2022
    Assignee: SKhynix Inc.
    Inventors: Duck Hoi Koo, Gun Woo Yeon, Young Ho Kim, Seung Geol Baek, Suk Ho Jung
  • Patent number: 11321011
    Abstract: A memory controller for controlling an operation of a device may include a command queue, a command queue controller, and a command information storage. The command queue may store a plurality of commands. The command queue controller may control an operation of the command queue using a pop signal and a push signal. The command information storage may store command information corresponding to each of the commands stored in the command queue. The command queue controller may control the command queue by checking the commands stored in the command queue based on the command information and converting the checked commands based on a result of the checking.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventor: Ho Jung Yun
  • Patent number: 11310317
    Abstract: A storage system is provided. The storage system includes a first storage cluster, the first storage cluster having a first plurality of storage nodes coupled together and a second storage cluster, the second storage cluster having a second plurality of storage nodes coupled together. The system includes an interconnect coupling the first storage cluster and the second storage cluster and a first pathway coupling the interconnect to each storage cluster. The system includes a second pathway, the second pathway coupling at least one fabric module within a chassis to each blade within the chassis.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: April 19, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Prabhath Sajeepa, Daniel Talayco, Qing Yang, Robert Lee
  • Patent number: 11288138
    Abstract: Recovery in a cloud-based storage system, including: receiving, by the cloud-based storage system among a plurality of storage systems synchronously replicating a dataset, a request to modify the dataset; generating recovery information indicating whether the request to modify the dataset has been applied on all storage systems in the plurality of storage systems synchronously replicating the dataset; and responsive to a system fault, applying a recovery action in dependence upon the recovery information indicating whether the request to modify the dataset has been applied on all storage systems in the plurality of storage systems synchronously replicating the dataset.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: March 29, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Joshua Freilich, Aswin Karumbunathan, Naveen Neelakantam, Ronald Karr
  • Patent number: 11281388
    Abstract: A method for managing a multi-system shared memory includes: upon receiving a data write instruction for writing data to the shared memory, acquiring a data size of to-be-written data that is to be written to the shared memory; judging whether the shared memory includes a data block that matches the data size and is idle; if the shared memory does not include the data block that matches the data size and is idle, acquiring a first data block that has a memory size greater than the data size and is idle, such that the to-be-written data is written to the first data block; acquiring a remaining idle space of the first data block after the to-be-written data is written to the first data block; and generating a new data block based on the remaining idle space.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 22, 2022
    Assignee: CLOUDMINDS (SHENZHEN) ROBOTICS SYSTEMS CO., LTD.
    Inventor: Yanfei Wen
  • Patent number: 11263143
    Abstract: A fabric controller is provided for a coherent accelerator fabric. The coherent accelerator fabric includes a host interconnect, a memory interconnect, and an accelerator interconnect. The host interconnect communicatively couples to a host device. The memory interconnect communicatively couples to an accelerator memory. The accelerator interconnect communicatively couples to an accelerator having a last-level cache (LLC). An LLC controller is provided that is configured to provide a bias check for memory access operations on the fabric.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Ritu Gupta, Aravindh V. Anantaraman, Stephen R. Van Doren, Ashok Jagannathan
  • Patent number: 11256617
    Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, in order to update the meta-data, the meta-data and host-data are separated and the only the meta-data is sent to the controller to be updated during a modified internal copyback operation. The host-data is not transmitted to the controller. While sending the meta-data utilizes resources of the communication link between the memory dies and the controller, it uses much fewer resources than if the host-data were also transmitted.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Zhengang Chen, Jianmin Huang
  • Patent number: 11256615
    Abstract: A memory system may include a memory device and a controller including a memory, suitable for generating map data for mapping between a physical address corresponding to data within the memory device in response to a command and a logical address received from a host, wherein the controller selects a memory map segment among a plurality of memory map segments, when a read count corresponding to the selected memory map segment is greater than or equal to a first threshold, calculates a map miss ratio of the memory using a total read count and a map miss count, and transmits the selected memory map segment to the host when the map miss ratio is greater than or equal to a second threshold.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11249648
    Abstract: Various implementations described herein relate to systems and methods for defining an optimal transfer and processing unit (OTPU) size for communicating messages for a plurality of non-volatile memory (NVM) sets of a non-volatile memory of the SSD. Each of the plurality of NVM sets corresponds to one of a plurality of regions of the non-volatile memory. Each of the plurality of regions includes a plurality of dies.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 15, 2022
    Assignee: Kioxia Corporation
    Inventor: Amit Rajesh Jain
  • Patent number: 11249915
    Abstract: Methods and systems are disclosed for populating a fail-over cache. When host computer systems in a system each have a content based read cache, the methods and system provide several functions applied in different orders for determining blocks that are to be included in the fail-over cache. Each function attempts a different strategy for combining the contents of the caches of each host computer system into the fail-over cache. If any strategy is successful, then the fail-over cache is placed into service. If all of the strategies fail, then an eviction strategy is employed in which blocks are evicted from each cache until the combination of caches meets a requirement of the fail-over cache, which, in one embodiment, is the size of the fail-over cache.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: February 15, 2022
    Assignee: VMware, Inc.
    Inventors: Vikas Suryawanshi, Kashish Bhatia, Zubraj Singha