Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

Abstract: A shift register includes a plurality of pulse generation portions for generating a series of pulse signals in response to a level change of inputted clock signals, and a plurality of shift pulse generation units. The plurality of shift pulse generation units has a predetermined shift pulse generation unit, with the predetermined shift pulse generation unit having a status signal generation circuit for outputting a first status signal to common wiring to which both of an earlier shift pulse generation unit and a later shift pulse generation unit are connected, and a clock supply circuit for supplying a clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit. In addition, there is a first period in which the clock supply circuit supplies the clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit and a second period in which the clock signal is not supplied.

Abstract: A technique for implementing an extended bit timer with a time processing unit (TPU), without using the channel hardware of the TPU includes a number of steps. A timer of the TPU is periodically read to determine the value of the timer. A counter is incremented when rollover of the timer has occurred and a coherency flag is de-asserted after the timer transitions through a first count. The coherency flag is asserted after the value of the timer transitions through a third count and the value of the timer is combined with the value of the counter to provide a current count. When the coherency flag is asserted and the value of the timer is equal to or between the first and second counts, the current count is adjusted.

Abstract: A device for automatic identification and counting of tagged articles massed together in a prescribed size bundles during linen cleaning and sorting processes. A three dimensional scanning of the bundles by multiple passes of a directional RF antenna oriented in different axial planes during each scan within a predescribed vertical path around the bundle.

Abstract: A self test for a counter system in an integrated circuit includes a clock coupled to counters in a plurality of counters. A first counter in the plurality of counters has a first counter output and a first counter rollover. A second counter in the plurality of counters has a second counter output, a second counter rollover less than the first counter rollover, and a second counter rollover signal that is active when the second counter has rolled over. A comparison circuit having inputs coupled to the first and second counter outputs, compares the first and second counter outputs to produce a counter error output signal. A latch latches the counter error output signal in response to the second counter rollover signal being inactive and the counter error output signal indicating a difference in the first and second counter outputs. Counters may be segmented to reduce a number of digits.

Abstract: The present invention provides for a divider circuit for reducing anomalous output timing pulses. A latch is coupled to the division selection line. A comparator is coupled to the division selection line. A first synchronizer coupled to the output of the latch. A frequency divider is coupled to the output of the synchronizer. A second synchronizer is coupled to the output of the comparator and the output of the frequency divider. There is feedback between the output of the second synchronizer and the enable input of the latch, the reset of the first synchronizer, the reset of the second synchronized, and the reset of the divide by n divider.

Abstract: A device for acquiring the maximum value (or the minimum value) of a multiplicity of measured values, having a multiplicity of measuring points for acquiring the measured values, an a data line for transmitting data values between the measuring points, at least one of the measuring points having a comparator for comparing a data value received on the data line with its own measured value, and being configured to transmit its own measured value on the data line only if said measured value is not smaller than the data value, wherein the data line is a serial line for transmitting the data value in the form of successive bits of decreasing significance, wherein the comparator is a serial comparator which compares the received bits of the data value with the identically significant bits of its own measured value, and wherein the measuring point is configured to transmit each bit of its own measured value which is detected as being larger than the corresponding received bit, until a comparison reveals that the bit

Abstract: The main circuit of each stage of the high-reliability shift register circuit is composed of transistors, and the turn-on time for the four transistors are only 1˜2 pulse time within one frame time. Transistors construct an inverter circuit which continuously offers a high-level supply voltage that controls activities of transistors so as to continuously offer a low-level supply voltage to the first node and the output terminal such that avoids the first node and the output terminal being in a floating state. Besides, one of the transistor acts as a charging circuit that extends the lifetime of another transistor. This circuit avoids the affection on the behavior of the shift register circuit that is caused by an a-Si (amorphous silicon) TFT under a sustained stress.

Abstract: A synchronous prescaler is provided that has an input line for receiving an input signal, which is synchronized to a low order dual modulus prescaler. The dual modulus prescaler generally divides responsive to a mode command line, but may have a dead-zone period where it may fail to respond to a generated mode command. The dual modulus prescaler also has an output line that is synchronized to an extender section. The extender section is used to further divide the input signal, and is synchronized to an adjustable counter section. A sync controller circuit receives an output from the counter section, as well as a timing signal from the extender, and generates the mode signal on the mode command line. In this arrangement, the sync controller generates the mode signal at a time when the low order dual modulus is in a condition to change divide modes, thereby avoiding providing the signal during the dead-zone period.

Abstract: A programmable frequency divider circuit with symmetrical output is disclosed. The frequency divider includes a non-symmetrical LFSR based component operated in series with a symmetrical divider component. Both the LFSR and the symmetrical divider may be programmed to provide flexibility. The frequency divider can dynamically adjust the divisor of the LFSR component to overcome limitations in the divide resolution due to the series combination of dividers, providing even and odd divisor values. The divider architecture can also provide higher level functions, including synchronization of multiple divider outputs, dynamic switching of divisor values and generation of multi-phased and spaced outputs. The linear feedback shift register (LFSR) component includes a feedback logic network decomposed into multiple stages to realize a maximum latch-to-latch operational latency of one gate delay regardless of the size of the LFSR.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: A portable device, such as a pedometer or other device having a display portion that may be separated from an attachment portion for easier viewing. When separated, the display portion remains connected to the attachment portion to facilitate ease of re-attachment and for maintaining both parts of the device in an interconnected relationship. The attachment portion is removably connectable to a wearer. The display portion is extendably and retractably connected to the attachment module. A spring biased spool is provided in the attachment module to take up and release line connecting the display module to the attachment module. The display module has a receptacle formed on the back thereof. The attachment module has a protrusion extending from a back thereof for mating engagement with the receptacle when the display module and attachment module are in a retracted position.

Abstract: Binary hysteresis equal comparator circuits and methods. An equal comparator does not indicate an equal condition until the two binary input values are exactly the same. However, after the two binary input values first become equal, a window of variation comes into effect, within which the first of the two values is allowed to vary while the circuit continues to report an equal condition. This window can extend only above the equal condition, only below the equal condition, or both above and below the equal condition. The width of the window is determined by providing one or two predetermined constant values, a first constant defining the amount of hysteresis provided above the second value, and a second constant defining the amount of hysteresis provided below the second value. Related methods are also described of performing equal comparisons while providing binary hysteresis.

Abstract: The present invention relates to a programmable frequency divider having one n-bit adder and one n-bit D Flip Flop. These are used to transform the import clock to the target clock. The adder takes one adjustment parameter and one return signal as a basis to create the first output signal, with the possibility to program the adjustment parameter. The D Flip Flop and the adder create a cycle, which is used to receive the first output signal and its import clock to create the second output signal. The second output signal is separated into a return signal and the target signal. The D Flip Flop sends the return signal back to the adder, which will make addition calculations under the adjustment parameter, finally giving out the target clock with the target signal as a calculation basis.

Abstract: A fault state detector for a ring counter is formed from unit current sources each switched under the control of a different one of the outputs of the ring counter. The currents switched in that manner are passed through a unit resistance to generate a voltage signal proportional to the number of asserted outputs from the ring counter. The voltage signal is compared to boundary reference values for valid states of the ring counter outputs and, if the voltage signal is not between the boundary reference values, a fault state is indicated.

Abstract: A fractional divide circuit for generating a periodic fractional clock is disclosed. A base clock is provided for generating a pre-divide clock at a base clock frequency with a period counter provided for counting cycles of the base clock. A select register stores constants that define parameters for a fractional divide ratio, there being at least four. A positive edge flip flop is provided wherein two of the constants are associated therewith. A negative edge flip flop is provided wherein the other of the two constants are associated therewith.

Abstract: Optimizing statistics counter use is disclosed. A total number of counter bits to be used to track two or more statistics is determined. The total number of counter bits is allocated among the two or more statistics to provide for each statistic a counter comprising the number of bits allocated for that statistic, the allocation being such that each counter overflows at a rate desired for that counter. The overflow rates may be balanced, such that each counter overflows at approximately the same rate.

Abstract: A frequency divider circuit (11) has an input port for an input signal (Fo) to be divided, an output port for a divided signal (FDIV), and means (12-19) for providing a variable division-ratio control signal (N+C) and a residual quantization error signal (R), applying the variable division ratio control signal (N+C) to a control port of the frequency divider, and using the residual quantization error signal (R) to cancel phase error in the divided signal. Both the variable division ratio control signal (N+C) and the residual quantization error signal (R) are dithered.

Abstract: An apparatus and method for counting wheel revolutions are provided that include a wheel-hub mountable odometer comprising an accelerometer comprising sensor means for sensing force, wherein the sensor means are operable to sense a force acting thereon and generate an electrical signal representative of said force. Further an electronic control system is provided comprising a microcontroller and power source, the microcontroller comprising electronic filtering means for attenuating irregularities in the signal from the sensor means and computing a wheel revolution count based on said attenuated signal, and output means for communicating the wheel revolution count. The accelerometer preferably comprises a dual axis electronic accelerometer with no internally rotating parts. Further, the output means preferably comprises at least one of a display means, an IR communication system, or a RF communications system.