Abstract: An improved method for counting irregular or unsymmetrical shaped articles that allows greater precision and provides enhanced features over current counting devices and methods. The method improves upon current devices and methods by providing a more precise volume for each article by using actual cross sectional areas of articles. The improved method also allows the user to count broken or incomplete articles as “partial” volumes. These partial volumes may be added to one another to give a precise total batch volume. The actual cross sectional areas may also be used to allow the user to display three dimensional adaptations of each article counted. Because this information is stored, the articles may be displayed at any time after the articles are scanned. The improved method also allows a user to determine the distance between articles, by using the counting device, and, using this information, adjust the feed rate of the device to an optimum feed rate.

Abstract: A frequency comparator circuit is configured to compare whether the frequency of two input signals are within a tolerance of each other. The frequency comparator circuit includes two counter circuits, an AND gate, and a frequency detector circuit that is configured to provide two reset signals. The two counter circuits are arranged to be clocked by a respective one of the two input signals, and further arranged to be reset by a respective one of the two reset signals. Further, the AND gate is arranged to perform an AND function on the overflow outputs of the first and second counter circuits to provide an status signal. If the status signal is high, the difference in frequency between the two input signals is less than the tolerance. If the status signal is low, the difference in frequency between the two input signals exceeds the tolerance.

Abstract: A shift-register circuit comprises an inverter and first to fourth transistors. The first transistor includes a gate coupled to an inverse clock signal, and a first source/drain coupled to a signal output from a previous-stage shift-register unit. The inverter includes a first input terminal coupled to the first source/drain of the first transistor. The second transistor includes a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to a clock signal, and a second source/drain coupled to an output terminal. The third transistor includes a gate coupled to a first output terminal of the inverter, a first source/drain coupled to the output terminal, and a second source/drain coupled to a first voltage. The fourth transistor includes a gate coupled to a signal output from a next-stage shift-register unit, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage.

Abstract: A multi-selection prescaler for dividing an input signal according to a ratio to obtain a desired frequency. The circuit has of a plurality of logic gates and D-flip-flops: a first frequency divider for receiving an input signal and generating a divided frequency; a second frequency divider connected to the first frequency divider for performing a further frequency division based on a selection switch having a plurality of selection signals and a plurality of AND gates; a module control for performing a logic operation on the selection signals and an external control signal (MC) by OR gates and being connected to the first frequency divider to control the divided frequency of the first frequency divider; and an output selection circuit connected to the second frequency divider for selecting output signal according to the selection signals.

Abstract: This invention describes a unique high-speed implementation for overflow detection logic to be used in high performance shifter functions. The overflow logic makes use of parallelism in combining shift value decoding and mask generation logic with the logic necessary to propagate data. Designs for both 16-bit and 32-bit shifters are presented and performance improvement of the new designs over conventional overflow detection circuits is demonstrated.

Abstract: Apparatus for counting sheets in stack (17) thereof and inserting tabs (27) between the sheets at predetermined counts, as well as a tabbing method, uses a rotatable counting disc (10) engageable with an edge region of the stack and including a sheet transfer slot (12) to transfer the next sheet to be counted from one face of the disc to the opposed face, upon rotation of the disc. There are means (30) to count the number of sheets transferred and also to advance the disc relative to the stack, as the counting progresses. A tabber (31) is arranged to insert a tab (27) between two sheets of the stack (17) when a predetermined sheet count has been achieved, which tabber (31) projects a tab in a generally radially outward direction with respect to the disc (10), immediately adjacent one face (13) of the disc and in a timed relationship to the rotation thereof.

Abstract: A shift-register unit. The first transistor includes a first source/drain coupled to a first terminal, a second source/drain, and a first gate coupled to a reset signal to stop the shift-register unit outputting a pulse signal. The second transistor includes a third source/drain coupled to the second source/drain, a fourth source/drain coupled to a second terminal, and a second gate coupled to a setting signal to initial the shift-register unit. The third transistor includes a fifth source/drain coupled to an output terminal, a third gate coupled to the second source/drain and a sixth source/drain coupled to a clock signal to start outputting the pulse signal. The fourth transistor includes a seventh source/drain coupled to the first terminal, an eighth source/drain coupled to the output terminal and a fourth gate coupled to a refresh signal to set a voltage level of the shift-register unit in a standby mode.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: Apparatus and method for generating a divided clock signal. A ring counter is provided with a sequence of output states. During steady-state operation, a different one of the output states is set at a first logical level and each of the remaining output states is set at a second logical level at each successive clock transition in a master clock signal. A gate network uses the respective logical levels of the output states to generate the divided clock signal. An error detection circuit outputs an error detection signal when a number of the output states at the first logical level is other than one, and proceeds to synchronously reset the ring counter when the error condition is detected. A programmable processor further asynchronously resets the ring counter in response to the error detection signal, as desired.

Abstract: A wristwatch-typed pedometer with wireless heartbeat signal receiving device includes a watch casing with a watch band for fitting to a user's wrist, a wireless heartbeat detector for detecting a heartbeat of the user and generating and transmitting a heartbeat signal wirelessly, and a pace signal sensor which is disposed in the watch casing for detecting a pace of the user and generating a pace signal. When a user puts on the wristwatch-typed pedometer and performs exercise, the heartbeat signal from the heartbeat detector is received by a wireless heartbeat receiving circuit of a control circuit and transmitted to a data processing unit. Moreover, the pace signal from the pace signal sensor is transmitted to the data processing unit via a pace signal receiving circuit of the control circuit. The data processing unit calculates and processes, and transmits the heartbeat signal and pace signal to a display unit for displaying.

Abstract: A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node &agr; is raised. When the potential of the node &agr; reaches (VDD−VthN), the node &agr; becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105.

Abstract: A bi-directional shift-register circuit for outputting data in different turns and reducing the power loss according to a low-voltage clock signal, a first directional signal, and a second directional signal.

Abstract: An improved fractional divider that comprises an integer value storage means containing the integer part of the division value ‘K’ connected to the input of a programmable counter means that is configured for a count value of ‘K’ or ‘K+1’ depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces the count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.

Abstract: A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.

Abstract: A digital counter that uses non-volatile memories as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter that keeps track of the less significant part of the count and a binary counter that keeps track of the more significant part of the count. The rotary counter implements a counting method that maximizes the count that can be obtained before the endurance limit of the memory is reached by making sure that each change of state of each cell is recorded as one count and that all cells in the rotary counter experience two change of state in every cycle. The binary counter records the number of cycles the rotary counter has gone through.

Abstract: A programmable-divider provides a lower-speed transition signal to effect a synchronized load of a new divisor value during a safe-load period of the programmable-divider, such that the division occurs using either the prior divisor value or the new divisor value, only. A combination of in-phase and reverse-phase counter stages are used to position the divisor-independent period of each counter stage so that an edge of at least one of the lower-speed counter-enabling signals occurs during a period when all of the counter stages are in a divisor-independent period. The preferred selection of in-phase and reverse-phase counter stages also maximizes the critical path duration, to allow for the accurate division of very high speed input frequencies.

Abstract: The dual-modulus prescaler circuit for a frequency includes several dividers-by-two of the asynchronous type, connected in series, a phase selector unit (11) inserted between two of the dividers-by-two (10, 12a) and a control unit for supplying first control signals(S0, S1, S2, C1, C2) to the selector unit as a function of a selected mode. Said control unit receives four signals phase shifted by 90° with respect to each other from a first master-slave divider and supplies a selected one of the four phase shifted signals. The selector unit includes a first amplifying branch (21) receiving two first phase shifted signals (F2I, F2Ib), a second amplifying branch (22) receiving two second phase shifted signals (F2Q, F2Qb), and a selection element (23) connected to each branch. The first control signals (S0, S1, S2) are supplied to the first and second branches, and to the selection element for selecting one of the four phase shifted signals (F2) at one output in a determined division period.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

Abstract: A revolution counter; includes a base body having a sensor arrangement and a power supply device which supplies energy to the sensor arrangement, and a rotary element connectable to a revolving member and rotating relative to the base body about a rotation axis. The rotary element includes a magnet arrangement, which so interacts with the power supply device that the sensor arrangement is supplied with energy during each revolution of the rotary element in at least three rotary positions of the rotary element regardless of a rotation speed of the rotary element to thereby allow the sensor arrangement to ascertain a rotary position of the rotary element. In order to prevent a transmission of mechanical forces from the rotary element to the base body, the rotary element is positioned with respect to the base body either without connection to the base body, or held by the base body at three-dimensional play.

Abstract: An asynchronous up-down counter includes a plurality of counter blocks. Each of the counter blocks has a counter output, an up-down control output, and an up-down control input. A counter signal output from each of the counter blocks has at least two bits. The asynchronous up-down counter also includes a signal bus coupling the up-down control output of a first counter block counting lesser significant bits to the up-down control input of a second counter block counting more significant bits. An up-down control signal output from each of the counter blocks has at least two bits. The up-down control signal may include a first control signal enabling counting operation of the second counter block and a second control signal indicating counting-up and counting-down.