Abstract: There is provided a register system of a microcomputer having a register that includes at least one register bit and having an additional storage arrangement allocated to the register and on which the data content of the register is able to be intermediately stored. To reduce the computing time for saving the data content of the register, while keeping the silicon surface required for the register system as small as possible, the additional storage arrangement includes at least one shift register having at least two shift register cells, the content of an arbitrary shift register cell being transferable into a register bit, and, conversely, the content of a register bit being transferable into an arbitrary shift register cell.

Abstract: A revolution counter includes a single sensor which scans movement of a rotary element and generates a raw signal commensurate with a rotary position of the rotary element for ascertaining one of at least three areas of angular ranges. Two of these areas include each a single continuous angular range, whereas a third area includes at least two angular ranges, which interrelate but are separated from one another. A power generation system delivers energy pulses to the sensor, when the rotary element rotates below a minimum value, so that a raw signal can be detected and the corresponding angular range area can be determined. The power generation system and the rotary element are so interconnected as to ascertain for at least part of the thus determined areas of angular ranges, by which of the angular ranges the rotary element is rotated, and to establish the number of revolutions based on the ascertained angular ranges.

Abstract: A machine used for digital counting which can provide multiple output counts. The machine is particularly useful in analog-to-digital (A/D) converters and in digital-to-analog (D/A) converters. The multiple output counts can change in different directions or in the same direction, and are generated using shared circuitry. The invention exploits properties of counting systems to allow A/D and D/A conversions in convenient digital number formats or in multiple different formats. The invention can be used in integrating converters to help eliminate errors such as comparator offset and dielectric absorption while converting and to increase the conversion rate.

Abstract: A method and apparatus for providing of normalizing a bit count is provided. The method comprises counting bits for a first frame, and normalizing a target bit in a target frame using the bits of the frame. The method then comprises counting to the normalized target bit in the target frame.

Abstract: Methods and systems for automatic generation of an at-speed binary counter are described. The binary counter includes a slow counter that increments when a fast counter overflows to keep up with a fast clock. A framework to automatically generate a Hardware Description Language (HDL) for an at-speed binary counter is also described.

Abstract: A counting device with control system includes a housing with a rotating wheel therein. The wheel includes a plurality of seats for each item to be counted. Upon deposit of the items into the housing, each item is seated for discharge through a housing aperture, past a sensor operating a counter and onto a conveyor line. A baffle adjacent the housing aperture directs the counted items to one or the other longitudinal side of the conveyor line. A control system controls the baffle position according to a preselected item count. An air pressure system assures a proper seating of each items and discharge through the housing aperture.

Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

Abstract: A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.

Abstract: A system, method and apparatus for comparing two floating point numbers is includes choosing a first floating point number and a second floating point number to be compared. The first number is sign extended one bit to create a first sign extended number. The second number is sign extended one bit to create a second sign extended number. The second sign extended number is subtracted from the first sign extended number to determine a subtraction result. The sign bits for said first number and said second number are examined to determine if they are both ones. If the sign bits for the first number and the second number are both ones, the sign bit of the subtraction result is inverted to create a final result. If the sign bit of the final result is a zero, asserting that the first number is greater than or equal to the second number. Alternatively, if the sign bit of the final result is a one, asserting that the first number is less than the second number.

Abstract: A pedometer including a pedometer body having a measuring mechanism that makes a measurement of a number of steps walked and a display that shows the measurement result; an illumination lamp and a battery installed in the pedometer body; a window provided in the pedometer body so as to allow the light of the illumination lamp to illuminate the outside of the pedometer body; and a power switch provided on the pedometer body and operable from the outside so as to turn on and off the illumination lamp.

Abstract: The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

Abstract: An integrated circuit according to the present invention includes application-specific circuitry and an embedded counter assembly capable of measuring the frequency of one or more clock signals, which may be generated internally by the integrated circuit or externally by one or more sources external to the integrated circuit. The embedded counter assembly utilizes a reference clock signal having known characteristics, and measures the frequency of an unknown clock signal based upon the reference clock signal. The embedded counter assembly is capable of measuring the frequency of internal clock signals that are otherwise inaccessible via external output pins.

Abstract: An apparatus and associated method is disclosed for increasing the maximum input frequency of a frequency divider system by altering the division ratio in the frequency divider system. In an exemplary form, the apparatus includes an electrical mixer circuit to combine an internal and an external frequency input signals into a combination frequency signal and a frequency divider circuit to receive the combination frequency signal and to frequency divide the combination frequency signal by a predetermined number, a signal splitter and a directional coupler in operative to receive the divided frequency signal and to generate an output frequency signal and a feedback frequency signal wherein the feedback frequency signal is identical in frequency to the output frequency signal and becomes the internally inputted frequency signal for the mixer. In this way the maximum input frequency of the frequency divider system can be advantageously increased.

Abstract: A counter circuit includes a plurality of flip flop circuits (FF circuits) sequentially connected for receiving a common clock signal, and two-input logic gates each having an input connected to an output of a corresponding FF circuit and the other input connected to an output of a common FF circuit, and of which output signal is supplied to an FF circuit positioned at the post stage of the corresponding FF circuit. A booby trap is realized by the two-input logic gates. The value input to each of the FF circuits is determined by logical operation of at most two logical values, so that the counter circuit can be adapted to the increasing frequency of a clock signal CLK. Thus, the counter circuit with the booby trap, capable of performing high-speed operation can be provided.

Abstract: A programmable frequency multiplier receives data representing a desired multiplication ratio from a first configuration register. The ratio data is transferred to the frequency multiplier concurrently with the generation of an internal delayed reset signal which holds all configuration registers in a reset condition until the frequency multiplier achieves a locked state. The configuration registers are dependent upon the internal clock signal generated by the frequency multiplier for proper operation. By causing the configuration registers to renew operation only after the stable frequency multiplier operation the danger of corrupting the information in the configuration registers is minimized.

Abstract: An electronic pedometer to accurately measure stride length of a walker includes a processing unit with an ultrasonic sound wave receiver attached to one foot and an ultrasonic sound wave generator attached to the other foot. Pressure sensitive switches close when each foot makes a step, providing signals to the processing unit to record the number of strides. The processing unit computes stride length by calculating distances using the ultrasonic sound waves.

Abstract: An apparatus and method for providing a high speed linear feedback shift register is disclosed. The high speed linear feedback shift register of the present invention comprises multiplexer flip flop circuits. The multiplexer gate on the input of each flip flop circuit is the only gate between each pair of flip flop circuits of the present invention. The linear feedback shift register of the present invention is capable of operating as a counter that does not need to be reset. The linear feedback shift register of the present invention may be used as a clock divider circuit.

Abstract: An Address Compare Circuit (1) allows for a large compare function at high speed due to its unique self-timed evaluation clock and bit compare circuits. The address compare circuit can reliably self-time off of the input data which insures proper compare timing with respect to the arrival of two address busses being compared. The HIT evaluation clock is generated by a circuit that has additional control inputs to increase the arrival times of input data, resulting in a greater operating window. This circuit provides a way to generate a very accurate internal HIT evaluation clock; therefore, the compare circuit reduces the extra setup time needed to guarantee all address data bits are valid. Furthermore, the HIT evaluation clock can be delayed to increase the arrival times of input data, resulting in a greater operating window.

Abstract: A conventional up/down Gray code counter has both a logic circuit section for up counting and a logic circuit section for down counting, and thus has a large circuit scale. To overcome this inconvenience, an up/down Gray code counter of the invention has a one-way Gray code counter that can count only in one, up or down, direction and a highest bit selecting circuit that receives the highest bit of the data output from the one-way Gray code counter and that then outputs the bit selectively either intact or after inverting it.

Abstract: A shift register has m stages which store one of two states, where m is an integer more than 1, each stage including clock input terminals at which n-phase clock signals are input, where n is an integer more than 1, and an input terminal, and an output terminal. The input terminal of one stage receives the signal delivered from an input terminal of the shift register or from the output terminal of the previous stage. The signal output at the output terminal of one stage is passed to the input terminal of the subsequent stage or to an output terminal of the shift register. Each stage receives an initial state level from one of the clock input terminals. The initial state level is used to initialize the state of each stage.