Abstract: A shift-register circuit. The PMOS transistor includes a first gate coupled to an inverse output signal output from a previous-stage shift-register unit, a first drain, and a first source coupled to an output signal output from the previous-stage shift-register unit. The first NMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the clock signal, and a second source. The capacitor is coupled between the second gate and the second source. The second NMOS transistor includes a third gate coupled to the first drain, a third drain coupled to the inverse clock signal, and a third source. The third NMOS transistor includes a fourth gate coupled to the first gate, a fourth drain coupled to the second gate, and a fourth source. The fourth NMOS transistor includes a fifth gate coupled to the first source, a fifth drain coupled to the second source, and a fifth source coupled to the ground voltage level.

Abstract: In one embodiment, as an example, N/M (=3.33333 . . . ) dividing is performed assuming M=3, N=10. That is, the frequency of the input signal CK is converted to the frequency of 1/3.33333 . . . times. Here, it is assumed that the frequency dividing number is 3.33333 . . . In this case, 3(=n) dividing is combined with 4(=n+1) dividing to perform the dividing, and accordingly a signal of a desired frequency can be obtained. In response to the output DOUT of the frequency divider, an n dividing counter counts the number of performed n-dividing operations and an n+1 dividing counter counts the number of performed n+1-dividing operations. An adder outputs the frequency dividing number (n) or (n+1). A frequency divider uses the frequency dividing numbers to divide an arbitrary frequency signal CK.

Abstract: An increasing monotonic counter over n bits formed as an integrated circuit, including an assembly of 2n+1?(n+2) irreversible counting cells distributed in at least n groups of 2p?1 counting cells, where p designates the group rank, and at least n?1 parity calculators, each calculator providing a bit of rank p, increasing from the most significant bit of the result count, taking into account the states of the cells of the group of same rank.

Abstract: A digital counter with a dial position having a hardware part which determines the n lowest-value bits of the dial position and a software part which determines the remaining higher-value bits of the dial position includes first and a second software parts as the software part with the dial position being a combination of the first software part and the hardware part when the hardware part is in a first counting range, and being a combination of the second software part and the hardware part when the hardware part is in a second counting range.

Abstract: A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base stages to another such that only one of the base stages is enabled at any give time. The enable bit has a pulse width of one clock cycle. The outputs from the base stages are grouped together by an OR gate to generate a single output that is a fraction of an input clock signal.

Abstract: A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a stage input of a first one of the delay stages. Each delay stages includes a stage input to receive a quotient signal, at least two paths having different associated path delays each coupled to receive the quotient signal from the stage from the stage input, and a multiplexer. The multiplexer is coupled to selectively communicate the quotient signal from one of the at least two paths to a stage output to select one of the stage delays.

Abstract: Printed products, such as newspapers are fed past a counting station arranged in imbricated fashion, preferably folded edges passing downstream first. A high intensity light source is arranged so that its light beams are oriented at an angle which, while illuminating upper surfaces of the newspapers, causes the forward folded edges to cast a shadow upon the upper surface of a downstream newspaper that the forward edge of the newspaper creating the shadow rests upon. An image sensing device creates an image of a given region which includes the leading edge of the newspaper creating the shadow. This image is compared with stored criteria to determine if the “shadow” is due to a leading edge of a newspaper and to thereby discriminate a newspaper leading edge from other spurious conditions which, although they may create a “shadow”, fail to meet the criteria of a leading edge of a newspaper.

Abstract: A friction roller paper currency counter. Specifically, the paper currency counter of the present invention incorporates electronic circuitry which automatically stops the mechanical motors in the event a foreign object is accidentally ingested by the counter.

Abstract: A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.

Abstract: An electromagnetic counter includes a case, an electromagnet, an anchor rotatable through magnetization and demagnetization of the electromagnet, and number wheels rotated by a predetermined angle according to the rotation of the anchor. A flexible board with a light emitting diode is disposed in a confined space in the case for illuminating the number wheels.

Abstract: Systems and techniques are disclosed relating to shifting a plurality of input data bits to the left or right by a number of bit positions as a function of a binary value of a plurality of shift control bits. A first shifter element may be configured to perform one of two shifting operations on the input data bits to produce a plurality of first output bits, a first one of the shift control bits being used to select the shifting operation performed by the first shifter element. A second shifter element may be configured to perform at least one shifting operation on the first output bits to produce a plurality of second output bits, each of said at least one shifting operation being selectable from two shifting operations, a different one of the shift control bits being used to select each of said at least one shifting operation performed by the second shifter element.

Abstract: A ripple counter circuit supports two modes of operation, a user mode and a test mode. In the user mode, the circuit functions as a standard ripple counter, counting in response to first edges (e.g., rising edges) on a clock input signal. In the test mode, the ripple counter circuit alternates between two states. In the first state, the bits all toggle from their initialization values to new values. In the second state, the circuit operates in the same fashion as the user mode. Therefore, the ripple counter circuit counts by one, returning all of the bits to their initialization values. This capability significantly simplifies the testing process, particularly for long ripple counters. Some embodiments of the invention include various control circuits coupled to provide an internal clock signal and/or an initialization signal.

Abstract: In a shift register and LCD device having the shift register that may be employed in the liquid crystal display device having a large screen size and a large resolution, the shift register includes stages cascade-connected with each other and each of the stages have a carry buffer for generating a carry signal. The pull-down transistor of each of the stages of the shift register is divided into a first pull-down transistor and a second pull-down transistor. A power voltage Vona larger than the power voltage Von applied to a clock generator is applied to the shift register. A signal delay due to the RC delay of the gate lines may be minimized, the shift register is independent of the variation of the threshold voltage of the TFTs, and image display quality may not be deteriorated.

Abstract: A system may include a control unit and a dual modulus prescaler. The control unit may generate a modulus control signal. The dual modulus prescaler may be configured to divide the frequency of an input signal by Q when the modulus control signal has a first value and to divide the frequency of the input signal by (Q+V) when the modulus control signal has a second value. Q is an irreducible fraction. The sum (Q+V) may be an integer or a fraction. The dual-modulus prescaler includes several clocked storage units (e.g., flip-flops) that are each clocked by a respective one of several equally spaced phases of the input signal. Each clocked storage unit operates in a toggle mode.

Abstract: A shift-register circuit. The input circuit receives the input pulse and outputs a high-voltage level input signal when the input pulse is at high voltage level.

Abstract: This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.

Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

Abstract: A fractional-N frequency synthesizer has a modulus controller with multiple inputs that control an initial output frequency of the frequency synthesizer, an increment of variation of tuning of the frequency synthesizer, and a difference between two adjacent output frequency settings. The fractional frequency synthesizer includes a modulus controller, which controls the modulus factor for a multiple modulus frequency divider. The modulus controller has a modulus selection circuit that provides a modulus control signal to the modulus divider to select the modulus factor of the modulus divider as a function of a sum of one input factor and a product of a second input and the gain factor. Control signal is an overflow from a continuous summation of the second digital data word and a product of the first digital data word and the gain factor digital data word repetitively with itself.

Abstract: A pedometer for detecting vibrations in a direction of motion is disclosed. The architecture of the device includes a main body, a vibration detector, and a counting circuit. The counting circuit is connected to the vibration detector and the counting circuit and vibration detector are installed inside the main body. Since the vibration detector is disposed orthogonal to the direction of motion, the vibration detector is able to detect the smallest vibration in the direction of motion and outputs a pulse signal to the counting circuit. The counting circuit includes a signal amplifier circuit, a signal detection circuit, and a processor. This pedometer is capable of picking up weak vibration signals to take an accurate count of the jogger's pace.

Abstract: A method for establishing a Gray code count sequence having N code words includes determining a first bit switch sequence having 2M−1 elements and a bit switching sequence property according to a first Gray code count sequence having 2M code words and where 2M is larger than N.A second bit switch sequence is determined having N−1 elements and the bit switching sequence property according to the first bit switch sequence. A second Gray code count sequence is determined according to the second bit switch sequence.