Abstract: It is an object of the present invention to make it possible to optionally configure various types of electronic counters. Therefore, the present invention is provided with a one-chip microcomputer 12 having a built-in ROM 13 and RAM 14 to write data corresponding to a variable on a program input through a communication port 10 and an interface 11 in the RAM 14.

Abstract: A counter is used to count tokens in a pusher-type game machine. The counter has a sensor unit (25) arranged in a path (23) through which tokens (19) fall. The sensor unit is a part of a capacitance sensor (51) for detecting a capacitance change in the path. A reference capacitance change corresponding to a single token failing through the path is stored in an MPU (47) in advance. A capacitance change detected by the capacitance sensor is compared with the reference capacitance change, to determine the number of tokens failing through the path.

Abstract: Non-power-of-two Gray-code counters, including modulos 10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register for storing an N-bit, e.g., 4-bit, Gray-code count. The count is converted to binary code by a Gray-to-binary-code counter. The resulting binary count is incremented by an N-bit incrementer that skips certain binary values by toggling least-significant bits in unison when indicated by certain most-significant binary bits. The result is converted to Gray-code by a binary-to-Gray-code translator. The translated result is stored in the register as the next count. An algorithm is disclosed for designing such a Gray-code counter for any even modulo. The modulo is expressed as a sum of positive and negative terms, each term being a power of two. The exponents of the terms determine the counter design.

Abstract: A frequency counter 1 includes a binary counter section 11 having a binary counter 20 for counting up frequency data, and a EEPROM counter section 12 having an EEPROM 40 containing frequency data. In a frequency count processing, frequency data of the EEPROM 40 are loaded into the binary counter 20. The binary counter 20 executes count up by a specified frequency on the loaded frequency data. The counted up frequency data are written into the EEPROM 40 to update the frequency data of the EEPROM 40. In one frequency count process, rewriting of the EEPROM 40 is completed once, which means that the number of time the EEPROM 40 is rewritten is reduced.

Abstract: A circuit arrangement as part of a shift register is proposed for controlling switch elements arranged in the form of a chain or a matrix, including four clock signals that are phase shifted by 90° with respect to one another for the control, with at least one transistor switching through a signal that is independent of the shift clock signals to the output to control the switch elements depending on the information to be shifted.

Abstract: A balanced dual-edge triggered bit shifting circuit includes a clock circuit to generate low skew, or edge-aligned, complementary clock signals, and a shift register that shifts a data bit in response to the complementary clock signals. The clock circuit is formed from two clock generators, each of which generates the edge-aligned complementary clock signals by alternatively coupling the input terminals of two buffer circuits to a voltage supply terminal and a ground terminal. Transfer gates coordinate the coupling of the input terminals of the buffer circuits so that the resulting output clock signals generated by each clock generator have clock transitions that are substantially simultaneous. The shift register is formed from at least one shift register stage that receives the edge-aligned complementary clock signals. The shift register stage includes two latching stages, each latching stage having an inverter with an output coupled to a latch circuit.

Abstract: A device for repeated registration of the number of thermal cycles to which a part for medical usage has been subjected has a temperature-sensitive element and/or a pressure-sensitive element arranged in conjunction with the part. This element reversibly changes its physical shape with temperature and/or pressure, variations in pressure being invariably associated with changes in temperature. A registration unit registers this change in shape when it exceeds a specific threshold value, as an indication of the part undergoing, or having undergone, a thermal cycle.

Abstract: A circuit for signalling if any like ordered bits Ak and Bk in first and second binary words differ comprises a comparator for each pair of like ordered bits and a common terminal. Each comparator includes first and second FETs arranged so: (a) the first and second levels of Ak are coupled to the common terminal via the first FET in response to Bk having the first value, (b) the first and second levels of Bk are coupled to the common terminal via the second FET in response to Ak having the first value, (c) the first FET decouples Ak from the common terminal and tends to cause the common terminal to be at the second level in response to Bk having the second value, (d) the second FET decouples Bk from the common terminal and tends to cause the common terminal to be at the second level in response to Ak having the second value, and (e) the common terminal is at the second level only in response to Ak Bk.

Abstract: The invention relates to dust/particle monitors, and particularly but not necessarily exclusively to a method of monitoring fine particles harmful to humans in working environments. Equipment and methods of detection are known but which have several disadvantages such as no instantaneous warnings of excessive exposure, bulky sampling equipment, prone to errors due to poor handling of particles, and fluctuating flow rates of air borne particles. The object of the invention is to provide a method and equipment that avoids those disadvantages mentioned above, an objective met by a method of monitoring dust/particulate material concentrations in air, comprising drawing air through a monitor at a predetermined rate to enable particles to pass through a measurement section one at a time, whereby they may be individually detected and counted.

Abstract: A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line includes a number of counter blocks, corresponding to the number of bits of the counter, connected in series. The low power counter blocks include memory devices consuming a minimum of power when they are disabled and activated only when the value of the respective data output connection has to be changed.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A semiconductor device is provided which has a plurality of output drivers whose slew rates are differentially controlled. The slew rates of the output drivers are controlled by a control means such that the slew rate of at least one of the output drivers is different than the slew rate of another output driver. Preferably, the slew rates are differentially controlled such that an output driver that drives a signal that reaches an output pin of a semiconductor package later slews at a faster rate than an output driver that drives a signal that reaches an output pin of a semiconductor package earlier. In this way all of the output pins of a semiconductor package can be driven to change states at approximately the same time. The slew rates of the output drivers can be differentially controlled through the utilization of programmable resistors.

Abstract: A system and method of implementing a digit counter having a plurality of digits, ranging from a least significant digit (LSD) to a maximum positional digit (MDP), is described. In one embodiment, the system comprises switching a single digit for each increment from the LSD to the MPD. Further, after the MPD is switched, for the next increment, resetting the digits from the LSD to the MPD, and moving the LSD and the MPD by one digit, such that the original LSD becomes a higher precedence digit.

Abstract: A frequency correction circuit includes a temperature sensor (100) disposed to measure temperature and produce temperature signals representing sensed temperatures. A data supplier (110) stores information items, receives digital input signals representing and produces a digital output information signal representing an item selected in accordance with the digital input signal. A control circuit (120) receives the temperature signals and receives the digital output information signal. The control circuit (120) produces control signals based on the temperature signals. A clock circuit (150) is disposed to generate a reference frequency signal. A digital synthesizer (130) receives the reference frequency signal and the control signals. The digital synthesizer produces an output frequency signal as directed by the control signals received from the control circuit (120).

Abstract: A method and apparatus for detecting a sinusoidal signal samples a received signal. An error signal generator receives at its inputs a previous sample of the received signal and a current sample of the received signal and generates an error signal based on these previous and current samples. A comparison circuit compares the generated error signal for the current sample to an error threshold value and generates a threshold comparison signal with a first value that indicates the generated error signal is below the error threshold value for a second value that indicates a generated error signal is above the error threshold value. A determination circuit then determines whether the received signal is a sinusoidal signal based on a threshold comparison signal generated for a plurality of samples. The determination circuit includes a counter that maintains a count of the number of threshold comparison signals having the first value within a sampling period.

Abstract: A delta-sigma modulator having a dead-zone quantizer and an error shaping digital filter clocked by a signal which is periodic at the frequency of the reference. A dead-zone quantizer provides quantization of a high resolution digital word to a low resolution digital word with three or a higher odd number of possible output levels and with an output of zero for an input near the center of the normal input range. The delta-sigma modulator is used in a fractional-N divider. The fractional-N divider is used in a fractional-N frequency synthesizer.

Abstract: The present invention is embodied in a system and method for using cascaded counters with a programmable branch and one or more event clocks that together provide the capability to generate clock pulses at high speed. Further, the programmable counter of the present invention is capable of generating a precise number of clock pulses within a very wide range of numbers.

Abstract: A time period (Td) is generated with a high accuracy and a high resolution. At a starting instant (ti) of the time period (Td), an analog integration operation (3) is started to generate an integration value (ios). At a certain instant (t1), the analog integration operation is interrupted to start counting (2) clock pulses (Clk). A selected number (N;N2) of clock pulses (Clk) is counted to obtain a sub-period (T2). The analog integration operation is resumed at the end of the sub-period (T2) at the integration value (ios) reached at the start of the sub-period (T2). The analog integration operation finishes at an end instant (td) of the time period (Td) at which the integration value (ios) crosses a reference value (Ref).

Abstract: There is provided a counter device comprising a master counter for counting an input signal applied thereto and a plurality of local counters disposed in a plurality of functional blocks, respectively, each for counting the input signal applied thereto, and for holding a count value corresponding to a plurality of bits of a count value of the master counter. A bus is disposed for each of the plurality of functional blocks to refer to remaining bits of the count value of the master counter.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.