Abstract: The pedometer having improved accuracy by calculating actual stride lengths of a user based on relative stride rates. The pedometer includes a waist or leg mounted stride counter, a transmitter for transmitting data to a wrist-mounted display unit, and a data processor for calculating necessary base units and actual stride rates and lengths. The pedometer can also interact with a heart monitoring device.

Abstract: A low power, low area shift register permits control over delay by dividing the shift register cells into a plurality of segments that are serially connected. A first selector provides data from a shift register input selectively to an input of one of the segments. A second selector provides data from an input or output of a selected cell of one segment of shift register cells to a shift register output.

Abstract: An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register. A plurality of pre-load flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop units and multiplexers. The PLFF circuits hold two initial LFSR sequence values. A load enable signal to the PLFF multiplexers and LFSR multiplexers is high for two input clock cycles. The present invention is capable of operating at high frequencies due to a shortened critical timing path.

Abstract: The present invention is an efficient system and method for flexible masking of output bits from a counter. The maskable counter system and method of the present invention modify the chain carry fed into a counter so that any bit (or bits) of the counter may be masked. A masked bit of a maskable counter system and method is utilized to facilitate user programmable control of multiple configurations in a memory. A maskable counter system comprises a mask register (e.g., a D flip flop), a counter (e.g., a D flip flop), and a masking coordination circuit. The masking coordination circuit permits a carry in signal, a carry out signal, and a counter output bit signal to operate in a normal incrementation manner if a mask bit is not asserted and prevents the counter output bit signal from changing if the mask bit is asserted.

Abstract: The present invention provides an automatic identification level control circuit, an identification level control method, an automatic identification phase control circuit, an identification phase control method, and an optical receiver, capable of stably setting an optimal identification level or identification phase. An automatic identification level control circuit of the present invention includes a coupling capacitor, an identification circuit, a level fluctuation detection circuit, an identification voltage control circuit, and a low-pass filter. The identification circuit includes limiter amplifiers and flip flops. The level fluctuation detection circuit includes exclusive OR circuits.

Abstract: A method for counting substantially uniformly sized objects includes the steps of obtaining an image of substantially uniformly sized objects; analyzing the image to determine total object area in the image and average object size of the objects; and determining a count of the objects from the total object area and the average object size.

Abstract: A score counter for sensing route of basketball shots includes a pair of photoelectric sensors installed at respective positions below an inner rim of a basket hoop to detect basketball valid shots. Such an arrangement overcomes basket net interference to the photoelectric sensors to avoid malfunctions and is capable of discriminating the correct route after a basketball is thrown into the basket hoop.

Abstract: A dual-modulus prescaler for a RF frequency synthesizer, which may operate in a high speed and reduce energy consumption with use of a selective latching technique includes a first frequency-dividing circuit for being synchronized to the clock signal to generate a latch control signal, latching the clock signal at a leading edge of the generated latch control signal, changing the frequency-dividing mode from a first frequency-dividing mode to a second frequency-dividing mode when latching the clock signal, and frequency-dividing and outputting the clock signal; a second frequency-dividing circuit for frequency-dividing the frequency divided signal from the first frequency-dividing circuit at a predetermined frequency-dividing ratio and outputting a plurality of frequency divided signals; and a logic operation circuit for logically operating a plurality of the frequency divided signals and the mode control signal to control the frequency-dividing mode of the first frequency-dividing circuit.

Abstract: A clock divider circuit having a fifty per cent duty cycle and multiple integer ratios for dividing an input clock signal. In one embodiment, a clock divider circuit may include a chain of serially-coupled flip-flops. The chain may include at least a first and a second flip-flop, both of which may be triggered by a first edge of an input clock signal. A third flip-flop, coupled to (but not part of) the chain may be configured to be triggered by a second edge of the input clock signal. The third flip-flop may be coupled to an output circuit. In addition to receiving the output signal from the third flip-flop, the output circuit may also receive signals from the chain of serially-coupled flip-flops. The output circuit may drive a second clock signal, which may be produced by dividing the first clock signal based upon the signals it receives. The first clock signal may be divided by an even or an odd integer ratio, or may be divided by an integer ratio (e.g. 2.

Abstract: A frequency divider and method for dividing a clock signal. The frequency divider including a first configurable signal generator, a second configurable signal generator, a data source coupled to the signal generators providing configuration data based on instructions received at an instruction port, a sequencer generating the instructions coupled between the signal generators and the data source and passing the instructions to the instruction port of the data source, and combining logic coupled to the outputs of the signal generators to produce the reduced frequency signal.

Abstract: A dispensing device for dispensing powder foods or liquids has a scoop for containing the powder or liquid, and levelling means for levelling off the scoop contents, wherein the levelling means co-operates with a counter such that operation of the levelling means is adapted to advance the counter, the counter being characterised in that the counter may be reset to zero in a single step process.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: A circuit for providing a function of a plurality of consecutive bits in a shift register is provided. The circuit includes a 2-input logic gate having a first input terminal connected to receive a bit being shifted into the shift register, and a second input terminal coupled to receive a bit being shifted out of the shift register. The circuit further includes a sequential logic device having an input terminal coupled to an output terminal of the 2-input logic gate, an output terminal that provides the function, and a control terminal coupled to receive a control signal for resetting the sequential logic device. In one embodiment, the 2-input logic gate is an exclusive OR gate, and the sequential logic device is a toggle flip-flop. In this embodiment, the function is a logical exclusive OR of the consecutive bits in the shift register. The function is implemented by initializing an output signal of the sequential logic device when the consecutive bits of the shift register have a predetermined value.

Abstract: An event counter circuit including an input signal coupled to a frequency divider circuit that can be cleared by an external signal, a multiplexer coupled to the divider circuit driven by an output edge and its inverse, and a counter circuit coupled to the multiplexer driven by outputs of the multiplexer.

Abstract: Oscillator control circuitry for a phase lock loop, including phase detection circuitry, control signal generator circuitry, bias control circuitry and charge pump circuitry. The control signal generator circuitry introduces specific and distinct time delays to the phase signals from the phase detection circuitry representing the phase difference between the reference and oscillator output signals. These time delays cause the bias control circuitry to enable and disable the output charge pump circuitry slightly before and after, respectively, those time intervals during which an output source (“pump up”) or sink (“pump down”) current is needed to drive the oscillator via the loop filter. This produces charge pump circuitry output signals with significantly faster rise and fall times and shorter pulse widths, thereby resulting in a charge pump output signal with higher SNR and reduced spurious signal energy.

Abstract: A dual-modulus digital prescaler circuit having an extended period in which responses to a divider control indicating a possible modulus change must be made, such extended period permitting higher speed operation while suffering no penalty in manufacturing cost or increased power use. In embodiments comprising a dual modulus divider, a fixed-modulus divider and interconnected control logic, dual modulus divider state transitions giving rise to incrementing of fixed-modulus divider states are selected to be independent of short-term instabilities in divider control inputs. Identified critical state transitions associated with output signals from the dual modulus divider are constrained to occur at times prior to periods of insensitivity to stability of the dual-modulus control signal. Thus, timing of such output signals is determined so that there will be following time interval sufficient to provide desired stability of the modulus control signal for the next divide cycle.

Abstract: A watchdog timer includes an instruction decoder, a delay circuit and a counter. The instruction decoder decodes a watchdog timer initialization instruction regularly executed to generate an instruction pulse for initializing the count of the counter. The delay circuit delays the rising edge of the instruction pulse, and supplies the delayed instruction pulse to the counter as a signal for initializing the count. The delay circuit prevents the pulse signal from being supplied to the counter when the operation frequency of the microcomputer is high or when the supply voltage to the microcomputer is low, so that the count of the counter overflows, and the overflow signal causes the microcomputer to be reset. This makes it possible to reset the microcomputer before it runs away, thereby solving a problem of a conventional watchdog timer in that the microcomputer can produce, if it runs away, an unexpected signal from its port before it is reset, and hence can impair the security of the system.

Abstract: In this invention compare circuitry is integrated into a serial shift register which can detect a bit pattern of any length with only the delay of three circuits being added to the shift of the last bit in the bit pattern. The circuitry is connected to operate either is a shift register or as a comparator for an N element bit pattern. Between adjacent registers in the shift register is a MUX used to select compare or shift register operation. An exclusive NOR circuit performs the compare between bits of the serial bit stream and reference bits of the pattern to be protected. An AND circuit accumulates the compare of a particular stage with the compare with the preceding stage. In the last stage the AND circuit provide an accumulated compare result of the preceding number of bit equaling in length the length of the bit pattern for which the compare is being performed.

Abstract: A filter on which living bacteria are captured is processed with an extraction reagent and a luminescence reagent. The state of luminescence of the filter is photographed by a television camera 1 including an optical system and an image acquisition means such as a charge coupled device. The number of luminous points is counted from data for the image of the luminous points of fluorescence originating in microbes through an image processing device 3 and a data-analyzing device 4. The result of the count is shown on a display 5. In the analysis of the data, when there exists a first luminous point adjacent to a second luminous point, the first and second luminous points are grouped and counted as one luminous point. A process for eliminating the effect of the diffusion of light from a luminous point of great luminance is performed.

Abstract: An assembly for generating a consecutive count includes an n-stage binary counter (24) incrementable by counting pulses in successive cycles and an EEPROM (10) in which an item of information representing the count achieved in each case is stored in the pauses between the cycles. The EEPROM (10) comprises n+1 memory cells. A control circuit (36) is provided causing the contents of the n−1 stages of the binary counter (24) assigned to the most-significant bits to be stored in the n−1 first memory cells of the EEPROM (10) and the contents of the nth or (n+1)th memory cell is changed in alternate cycles.