Abstract: An apparatus for eliminating noise is disclosed. The present invention includes a counter, which counts in a first direction when an input signal is active, and in a second direction otherwise. A determining device is used to determine a predetermined first threshold value, and assert an output signal while such value is reached. The present invention also includes a limiting device, which prevents the counter from counting beyond or below a predetermined limit value.

Abstract: A low jitter fractional divider with low circuit speed constraint is disclosed, which lowers the frequency of a high frequency clock signal to perform a fraction division in the condition of low frequency. A compensation circuit, which has an adjust buffer and a down-counter, is provided for adjusting the output clock signal of the fractional divider to have a jitter substantially equal to the jitter occurred in high frequency, such that a low jitter can be achieved without being limited by the circuit speed.

Abstract: A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.

Abstract: The invention herein provides a supervisory circuit which is adapted to monitor an input signal and produce as an output signal, a parametric signal corresponding to the input signal. The circuit includes an input for receiving the input signal, and a stochastic processor coupled to the input for receiving the input signal and processing it to derive a signal that represents a parametric measure of the input signal. An output connected to said stochastic processor provides the parametric output signal as an output for supervisory purposes.

Abstract: A five sided chamber is placed in a laundry chute such that any laundry article passing through the chute must also pass through the chamber. The five sided chamber is mirrored on the inside surfaces of four of the five sides while the fifth side is transparent. A light beam emitter and a light beam receiver are positioned along the transparent fifth side of the chamber. The light beam emitter is directed at the center of one of the four mirrored sides and the light beam receiver is directed at the center of an adjacent one of the four mirrored sides. Reflection of the light beam internally within the five sided chamber is such that the light beam forms a star pattern before returning to the light beam receiver via the transparent fifth side.

Abstract: Apparatus and method for testing an optical encoder used to determine position of a moveable member. The optical encoder supplies a first binary signal indicative of a position of the moveable member and a second binary signal indicative of the position. The first binary signal and the second binary signal are in quadrature relationship. The apparatus has a first delay device connected to receive the first binary signal. The first delay device produces a first delayed binary signal. The apparatus also includes a first logic gate connected to receive the first binary signal and the first delayed binary signal. The first logic gate produces a first edge detection pulse signal. The apparatus further includes a second delay device connected to receive the second binary signal. The second delay device produces a second delayed binary signal. The apparatus further includes a second logic gate connected to receive the second binary signal and the second delayed binary signal.

Abstract: A delay time compensation circuit for a clock buffer includes first and second toggle flip-flops multiplying an input clock signal and a delay clock signal which is delayed by an input buffer, respectively, a time interval extraction chain extracting a time interval between a rising edge of the input clock signal and a rising edge of the delay clock signal in accordance with clock signals multiplied in the first and second toggle flip-flops, and a variable delay chain delaying the input clock signal by a time interval extracted from the time interval extraction chain. The circuit employs a ½ multiplied clock signal and operates without regard to a duty cycle of an input clock signal, thereby compensating for all the delay time within the cycle of the input clock signal.

Abstract: Disclosed is a delay circuit for delaying at least the timing of a rising edge or the timing of a falling edge of an input signal alternating between first and second levels. The delay circuit includes (1) a charge pump in which first and second field-effect transistors of different channels are serially connected; (2) a capacitor connected in parallel with the first field-effect transistor; (3) a charging current control circuit for passing a charging current into the capacitor via the second field-effect transistor of the charge pump when the input signal is at the first level; (4) a discharge current control circuit for releasing a discharge current from the capacitor via the first field-effect transistor when the input signal is at the second level; and (5) a discrimination circuit for outputting a signal of a prescribed logic level based upon a terminal voltage of the capacitor.

Abstract: A lap counting mechanism is described for a race-track for toy cars of the type in which the cars are guided in slots. The guide member of the car, which in use is received within the slots, is provided with a left-right asymmetry and the lap counting mechanism is able to detect this asymmetry. This allows at least two cars to be clearly distinguished by the lap counting mechanism and so the number of laps that an individual car has done may be totaled accurately even though the cars may swap tracks and slots. The sensing means and the associated asymmetry may be electrical, optical or magnetic. Means are also provided for detecting the speed of the cars and for generating sound and light effects.

Abstract: Disclosed is a system and method to compare logical values. The system employs a field programmable gate array (FPGA) configured for comparing logical values. The FPGA includes a number of inputs to receive an N-bit sampled value from a target system, where N defines the number of bits in the N-bit sampled value. The FPGA also includes a number of lookup tables configured to receive an M-bit portion of the N-bit sampled value. These lookup tables generate a lookup table output in response to the M-bit portion. Finally, an AND operation is performed on the outputs of the lookup tables that generates an output indicating whether the particular N-bit logical value matches a particular desired value. Note that a single AND gate may be used or a number of AND gates may be used in place of the single AND gate. The tables within the lookup tables are generated based upon a desired logical value and a comparison mask value.

Abstract: An event counter is disclosed which, in one embodiment, provides a reaction timer to time a user's response time to an event. In a second embodiment, the event counter provides a counting device to count the number of occurrences of events or the magnitude of an event. The invention uses a commercially available stopwatch to time the response time. The start/stop switch of the stopwatch is connected to a signal generator such as a piezoelectric element. In one variation, the internal piezoelectric element used as a beeper in the stopwatch is used as the signal generator. In a second variation, the event timer is further provided with a circuit to allow a higher voltage LED to be driven by a lower voltage of the system battery. In yet another variation, the event timer further includes a random delay circuit to randomly delay the start time of the stopwatch. Random delay is provided without a microprocessor by using a variable current switch and two RC circuits having different tau values.

Abstract: A reset device is disclosed which is part of a micro-controller formed on an integrated circuit. The reset device has a counter which outputs a count enable signal after counting a predetermined number of counts. In response to an input reset signal, an input device of the reset device provides a start signal to the counter for initiating count-down thereof. An output device outputs an output reset signal in response to the start signal and the count enable signal. The start signal is inhibited by a control signal, which is provided from a control device in response to an external reset signal received at an input pin of the micro-controller. The input device includes an AND gate which receives the input reset signal, an inverted delayed version of the input reset signal, and the disable signal. The reset device further includes an OR gate which receives the start signal and the count enable signal to provide an input signal to the output device for generation of the output reset signal.

Abstract: By utilizing a plurality of charge storing elements, a delay circuit may be reduced in size and cost. A delayed output signal is produced a predetermined time period after detection of an input signal by selectively charging and discharging each of a plurality of charge storage units either concurrently or successively and by detecting the charge level of each respective charge storage element. When the charge level of the respective charge storing elements indicates that a predetermined period of time has transpired since detection of the input signal, a delayed output signal is generated. This operation is performed in one embodiment by simultaneously charging two capacitors, comparing the voltage level of one capacitor with a reference potential, and inverting an output signal when the level reaches the predetermined reference potential. The second capacitor is used to tie the output to this level while the first capacitor discharges.

Abstract: A comparator compares a first data word with a second data word. The comparator includes a first stage of two input XOR gates, each of which receive one bit of the first word and a corresponding bit of the second word, and output a coincidence detection signal. A first inverter circuit receives a control signal and generates an inverted control signal. A decision circuit receives the inverted control signal and each of the coincidence detection signals, and generates a decision circuit output signal which indicates when any one of the coincidence detection signals is active. A two input NAND gate receives the decision circuit output signal and the control signal and generates a comparator output signal. The decision circuit includes an inverter circuit that receives the inverted control signal from the first inverter circuit and a series of transistors connected between the inverter circuit output terminal and ground. The gates of the transistor receive the respective coincidence detection signals.

Abstract: The pedometer having improved accuracy by calculating actual stride lengths of a user based on relative stride rates. The pedometer includes a waist or leg mounted stride counter, a transmitter for transmitting data to a wrist-mounted display unit, and a data processor for calculating necessary base units and actual stride rates and lengths. The pedometer can also interact with a heart monitoring device.

Abstract: The pulse counter counts high speed pulses and detects an absolute phase difference among a plurality of electric motors. Pulse outputs 5 and 6 from pulse generators 3 and 4 are inputted into integrating counters 15 and 16 through pulse converters 9 and 11 and rotation direction detectors 10 and 12. Integrating counters 15 and 16 count up/dow the pulses in response to the rotation direction. Integrating counters 15 and 16 are cleared with a zero phase pulse output 7, outputted per revolution from the pulse generators 3 and 4. Multipliers 19 and 20 multiply outputs from the integrating counters 15 and 16 by a ratio set by a coefficient unit, and output a signal corresponding to the rotation angle of each electric motor. Adder/subtractor 21 estimates a deviation between the outputs of the multipliers 19 and 20 such that the phase difference between the pulse generators 3 and 4 is estimated.

Abstract: In an FET device having a pair of input terminals, a pair of output terminals, a plurality of FETs and driving circuits, the driving circuit has such a circuit structure that source electrodes of the FETs are electrically connected to each other. Each of gate electrodes of the FETs is independently connected to a photo-diode array. The gate electrodes of the FETs are not electrically short-circuited to each other. The FETs are tuned on and off in response to a single control signal.

Abstract: The present invention relates to a circuit including at least one analog processing cell having a time constant determined by a capacitor and a resistor. A calibration circuit comprises a bridge formed of a switched-capacitance resistor and of a resistor adjustable by means of a digital control signal; and a feedback loop to adjust the digital control signal so that the voltage at the midpoint of the bridge is equal to a predetermined fraction of the voltage applied across the bridge. The resistor of the processing cell is also adjustable by the digital control signal.

Abstract: A buffer design for use in digital signal processing for providing parallel shifting of digital data and serial output of the shifted data. The buffer includes an input shift register for receiving and shifting an input digital word, and one or more parallel shift registers connected to the input shift register for receiving and parallel shifting the shifted digital word output by the input shift register. An output shift register is connected to the parallel shift registers for shifting and serially outputting the shifted data word. The use of parallel shift registers in the inventive buffer allows for a more efficient use of chip surface area in the buffer design, thereby increasing overall chip yield and reducing chip cost.