Abstract: The invention includes a particle sensor with a particle counter. A regenerative blower pulls ambient air into a flow within the particle counter, and a laser illuminates the flow to generate laser radiation indicative of particles within the flow. A detector detects the laser radiation; and particle sensing electronics counts particles within the flow at a preselected volumetric flow rate, e.g., 1 CFM. Preferably, the particle counter includes a plurality of pressure sensors; and a blower speed voltage controller adjusts the speed of the blower according to signals from the pressure sensors to achieve the preselected volumetric flow rate. The regenerative blower permits use of a high efficiency exhaust filter to filter air exhausted from the blower. An airflow path between the particle counter and the regenerative blower preferably has at least one bend between the particle counter and the blower to increase compactness of the system.

Abstract: A system for counting a series of progressively moving articles using one or more sidewardly positioned and angularly oriented ultrasonic transducers which bathe the articles with ultrasonic waves and receive echoes reflected backwardly therefrom. Distances to the articles are determined by measuring round-trip sonic travel times. Count adjustment signals are generated when articles pass through the fields of view of the transducers and are replaced by other articles at measurably different distances.

Abstract: The present invention provides a method of processing signals of encoders and an apparatus employing the same by each of which increase and decrease of a counter value can be made to match an angle of a rotational angle of two-phase incremental encoders all the time.

Abstract: A frequency divider circuit, and a digital PLL circuit including the same, which can suppress jitter occurring in an output signal, including a first circuit module which drives D-FFs connected in series using an input signal as a reference clock signal and divides the input signal by a frequency division ratio selected by a frequency division ratio determining signal to produce a first divided signal; a second circuit module which drives D-FFs connected in series using the first divided signal as a reference clock signal and divides the first divided signal by a frequency division ratio corresponding to the number of D-FFs connected in series to produce an output signal; and an OR circuit which produces a frequency division ratio determining signal based on the outputs of the D-FFs of the second circuit module and a frequency division ratio selecting signal.

Abstract: An AC-coupled driver comprises a drain output stage in which the quiescent-state current is set by a current mirror, and by a bias current for the current mirror. The drain output stage includes a DC coupling connected to the current mirror by a capacitive-resistive network. The DC coupling allows the drain output stage to deliver a high current following input of an AC voltage signal into the AC-coupled driver.

Abstract: A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter for monitoring a number of specified events. A data storage device is coupled to the counter for loading the counter with counter values for each of the contiguous counts. A control logic circuit is coupled to the counter and to the data storage circuit for loading the counter and the data storage device with the counter values.

Abstract: A method and apparatus for determining the number of particles or cells in a liquid sample. The method comprises a) determining the number of particles or cells in a first volume of the liquid sample, b) determining the statistical uncertainty of the determined number of particles in said first volume, c) if the determined uncertainty is larger than a pre-determined value, determining the number of particles or cells in a further volume of the liquid sample, d) adding the numbers of cells or particles determined in steps a) and c), e) determining the statistical uncertainty of the number of particles determined in step d), f) repeating steps d) and e) with a further volumes of the liquid sample, until the uncertainty determined in step e) is lower than said pre-determined value or until a pre-determined total volume of the liquid sample in which the number of cells or particles has been determined exceeds a pre-determined volume being larger than said first volume.

Abstract: In systems embodying the invention X clock signals having the same frequency, with each clock signal having a different phase, are supplied to the inputs of a multiplexer whose output is connected to the input of an "integer" frequency divider circuit; where X is an integer greater than 1. The mulitplexer is controlled to selectively supply different ones of the X clock signals to the frequency divider circuit for producing at the output of the frequency divider circuit a signal whose frequency is a function of the divider ratio of the frequency divider circuit and the sequencing of the clock signals supplied to the frequency divider circuit.

Abstract: A prescaler circuit for a frequency synthesizer includes two circuit blocks, each having an OR gate coupled with a master-slave flip-flop. An input clock signal having a frequency FN is supplied to the flip-flop of each circuit block, and an output clock signal having a frequency FN/2 or FN/3 is generated in response. A control signal supplied to the OR gate of the second circuit block determines whether the frequency will be divided by 2 or by 3. The circuit blocks generate differential output signals, and common-mode signals are generated for supply to the OR gate inputs by summing and dividing the differential output signals with high value resistors.

Abstract: An efficient charge pump circuit. Increased efficiency compared to previous pump circuits is achieved through use of a novel charge transfer switch and associated clocking scheme which reduces the supply current required to operate the charge pump. Instead of repeatedly charging and discharging a stray capacitance of each pump stage capacitor, some of the charge stored in the stray capacitor on the clock driver side is transferred to the next pump stage. This serves to pre-charge the stray capacitor of the next stage, reducing the supply current required to operate the charge pump. The apparatus and method described can also be used to reduce the power consumed by a system or circuit which has internal signals or nodes which are in opposite phase to each other. This is accomplished by reducing the power used to charge and discharge a stray capacitance associated with the signals or nodes.

Abstract: The present invention is an N-nary equality comparator that receives as inputs two 32-bit 1-of-4 operands. The equality comparator generates an "equal" indicator if the values of the two operands are equal. The equality comparator generates a "not equal" indicator if the values of the two operands are not equal.

Abstract: A delay circuit is disclosed which includes first level transition unit for receiving an input signal having more than two different logic levels and varying the pulse width of the signal, and second level transition unit connected with the first level transition unit for varying a pulse width of a signal inputted, whereby the delay circuit delays an output signal from the second level transition unit, wherein said first and second level transition unit includes an inverting unit for inverting an input signal, a MOS transistor having its gate electrode receiving the input signal and its first and second electrodes receiving an output signal from the inverting unit, a resistor connected between the first electrode and the second electrode, and a capacitor connected between the second electrode and a ground.

Abstract: Control circuit for providing the greater of a supply voltage V.sub.CC and a battery voltage V.sub.BATT. A comparator compares V.sub.CC and V.sub.BATT, and provides output signals to an inverting gain stage. A switch receives output signals from the inverting gain stage and provides the greater of V.sub.CC and V.sub.BATT as the circuit output and as the comparator supply voltage. The circuit output voltage rapidly switches between V.sub.CC and V.sub.BATT as the comparison status of the two voltages changes.

Abstract: In order to prevent the value of a flipflop from being indefinite during a period from a power-on time to the time a first clock signal is inputted, a reset circuit for a flipflop is configured to supply a clock to a clock input terminal of each of flipflops at the power-on time, so that an output of each flipflop never becomes indefinite. For example, in the case that an input/output of tristate buffers coinected in common to the same bus are controlled by a corresponding number of flipflops, respectively, a pass-through current caused for an output collision on the bus can be prevented with a relatively small scale of circuit.

Abstract: Multiple controllable delays reduce EMI radiated during the transmission of multiple synchronized signals. Each controllable delay introduces a controlled delay into a corresponding signal being transmitted. The controlled delay is such that the combined strength of the multiple signals at peak frequencies is substantially reduced. This results in reduced EMI radiation at those peak frequencies.

Abstract: A wheel mounted data logger has an odometer for mounting at a hub of a wheel of a vehicle and response to turning of the wheel, an hourmeter for mounting on a structure of the vehicle and response to running of an engine of the vehicle, and microcontroller for mounting on the vehicle and receiving, recording and transmitting the responses of the odometer and hourmeter. The odometer, hourmeter and microcontroller are mounted on the vehicle as a unit preferably by adhesive.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: A device for counting the number of corrugated articles in a stack of corrugated articles includes a light source for illuminating a multi-article containing surface of the stack of corrugated articles. An electro-optical image capturing camera captures a first visual image frame of a first segment of the multi-article containing surface, and a signal converting means converts the first visual image frame into a first electronic frame signal representative of the first visual image frame. A central processing unit, a frame grabber circuit and software process the first electronic frame signal into a first series of article signals representative of the series of individual articles of the first segment of the multi-article containing surface. The processor also counts the number of individual articles in the first series of article signals.

Abstract: The electronic circuit contains dual edge triggered flip-flop, which loads data on both the rising edge and the falling edge of a clock signal. The clock signal is supplied by a clock supply circuit with an enable input and a source input for receiving a source signal. The clock supply circuit toggles the clock signal as from an earliest available edge of the source signal after the enable signal at the enable input switches to an active state, irrespective of a polarity of said earliest available edge.

Abstract: The invention relates to a wave form shaping circuit, which outputs signals after shaping the input signal to a duty 50% wave form regardless of whether or not input signals are of duty 50%, wherein a duty determination circuit is provided, which determines and instructs the timing position of duty 50% of clock signals to be outputted, upon receiving a timing signal prepared by a timing generation circuit 2.