Abstract: A rendering device for converting input information into a bit map including a Bezier subdivision processor responsive to Bezier curve information describing a Bezier curve of an image. The Bezier subdivision processor performs at least one subdivision on the Bezier curve if the Bezier curve is greater than a desired resolution of a bit map to produce subdivided Bezier curves until all subdivided Bezier curves are at about the resolution of the bit map. The Bezier subdivision processor produces cross information from each Bezier curve which makes one crossing of a grid having the resolution of the bit map. The rendering device also includes a digital processor responsive to the cross information and operative to produce a bit map of the image from the cross information.
Abstract: A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.
Abstract: A fully testable CMOS comparator circuit is disclosed having INV and NAND logic gates which form data paths for propagating data through the comparator circuit. The data propagated through the comparator circuit include greater-or-equal signals. The comparator is fully testable because there are no redundant circuit elements.
June 18, 1997
Date of Patent:
April 4, 2000
International Business Machines Corporation
Bruce Conrad Giamei, George Anthony Sai-Halasz
Abstract: A device for counting the number of usage cycles of a sensor, for intracorporeal electrophysiological measurement and/or therapy, has a counting unit, connected to the sensor, containing a specific identification code for the sensor, and a detection unit which detects the sensor's connection/disconnection to/from external measurement and therapy equipment. The detection unit causes a sensing unit to read a sensor identification code in the counting unit whenever the sensor is connected so as to determine, from information about sensor usage stored in a main computer, whether conditions for a new usage cycle have been met and, if so, increments the counter's contents by one usage cycle.
Abstract: A programmable divider or prescaler divides an input signal by a divisor of two raised to the m.sup.th -power plus one, (2.sup.m +1), where m is an integer, and n is a value between zero and two raised to the m.sup.th -power minus one, (2.sup.m -1). When m is equal to 3, the duty cycle is between 44% and 56%. The divider can be utilized in communication applications for providing radio frequency source signals. The duty cycle is maintained around 50% for use with balanced mixers.
Abstract: The device for electronically simulating a component position includes a first counter (40,42) which counts counter pulses (Zt) determined by respective occurrences of a periodic event marking respective component positions; a second counter (30) which, in response to occurrence of a first event (e2), starts a third counter (34) which counts at a counting rate faster than that of the second counter (30) so as to repeatedly run through a predetermined value range (Z') until occurrence of a subsequent event (e3) and which produces a basic clock pulse (Co) each time a final value (y) of the predetermined value range (Z') is reached; and a readjustment circuit (38) which produces the counter pulses (Zt) from the basic clock pulses (Co).
May 15, 1995
Date of Patent:
November 2, 1999
Robert Bosch GmbH
Mathias Lohse, Frank-Thomas Eitrich, Patrick Hynes
Abstract: Digital counter register stages are constructed as two-to-one mux registers, each employing a multiplexer stage having first, second, and third inputs and an output connected to the switching signal input of a D-type flip-flop, whose Q output comprises a first input to the multiplexer stage. An inverter buffer is associated with each register stage and has an input connected to the output of said D-type flip-flop and an output connected to the second input of the multiplexer stage and fed forward to a NOR gate associated with each subsequent register stage. The output of the NOR gate comprises the third input to the multiplexer stage of the associated register stage.
Abstract: A flip-flop includes non-volatile storage of a bit for encryption purposes or other applications. The non-volatile bit remains in the flip-flop, substantially unaltered, irrespective of normal flip-flop operation, and is available to be recalled whenever it is needed. The flip-flop is implemented using a pair of CMOS cells. Each cell includes a floating gate formed by connecting the gates of an n-mos transistor and a p-mos transistor. One of the two floating gates is selectively charged by hot electron injection, thereby raising the threshold of that cell. Depending upon which of the two cells is programmed by this process, the flip-flop outputs a logic one or a logic zero during a recall mode.
Abstract: A frequency divider (50) comprises complementary components (e.g., CMOS transistors) which are placed in two complementary portions (10, 20) with similar structures. The portions are coupled by four lines (131-134). Each line (e.g., 131) is coupled to a pair of transistors including a pull device (e.g., 271) and a hold device (e.g., 291). The devices receives identical signals from another line (e.g., 134) and the input signal X in the same, non-inverted form. The devices have complementary logical functions because of their complementary structures (serial.backslash.parallel) and complementary components (P-FET, N-FET). When a line (e.g., 131) is pulled to a reference line (e.g., 91), contention between the devices is substantially avoided. There is no need to provide the input signal X in a non-inverted and in an inverted form.
Abstract: A frequency dividing circuit, which is easy to form as an IC and which offers reduction both in size and power consumption, has a register "a" for storing the difference between the denominator and the numerator of the fractional frequency dividing ratio, another register "b" for storing the numerator of the fractional frequency dividing ratio, a selector for selecting one of the registers and connecting the selected register to a computing unit, a flip-flop for picking up the output from the computing unit in timing with the signal to be frequency-divided, a comparator for comparing the value stored in the register "a" and the value held by the flip-flop, and a logical circuit for computing AND of the output from the comparator and the signal to be frequency-divided.
Abstract: Power consumption is reduced in a semiconductor integrated circuit. In a conventional flip-flop circuit, there is a transistor between one side current electrode of a PMOS transistor (PTr7) and an node (V0) of a power source. This transistor is deleted and one side current electrode of (PTr7) is connected to an node (D2). In a similar manner, one side current electrode of (PTr13) is connected to an node (D13), one side current electrode of an NMOS transistor (NTr6) is connected to an node (D6), and one side current electrode of (NTr14) is connected to an node (D12). Thus, by deleting transistors, the capacity of transistors which are to be driven by a clock signal is reduced, and therefore, power consumption is reduced.
Abstract: A semiconductor unit is composed of an analog unit, a digital unit, a signal line through which a signal is transmitted from the analog unit to the digital unit, an electric source line Vdd1 through which a high voltage is applied to the analog unit, an electric source line Vdd2 through which the high voltage is applied to the digital unit, an electric source line Vss1 through which a low voltage is applied to the analog unit, an electric source line Vss2 through which the low voltage is applied to the digital unit, and a protective circuit arranged between the electric source lines Vss1 and Vss2. The protective circuit functions to electrically connect the electric source line Vss1 and the electric source line Vss2 in cases where an electric potential difference between the electric source lines Vss1 and Vss2 exceeds a prescribed value. Similar protection can be provided between the high voltage source lines Vdd1 and Vdd2 or between the signal line and the second source lines Vdd2 and Vss2.
Abstract: A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read data signal. The present invention generally comprises a three-level receiver, a latch and an output driver to form a one-pin bidirectional interface used with a shift register. To write, the interface converts a three-level input signal into separate clock and data signals which drive the shift register. To read, the interface converts a bi-level input signal into a three-level output signal representing the output of the shift register. As a result, the present invention allows the programming of a device such as an erasable programmable read only memory (EPROM) in a clock chip while utilizing the fewest number of pins.
Abstract: A system is provided for generating an accurate and stable output clock signal of a desired output frequency in response to a system clock signal having a system clock period. The system uses an accurate and stable reference clock signal. The system comprises a measuring circuit and a ratio counter. The measuring circuit receives and processes the system clock signal and produces a measurement, referred to as the system clock measurement, that is indicative of the system clock period. The ratio counter receives the system clock signal and the system clock measurement and generates the output clock signal. The system is resistant to noise in the output clock signal caused by asynchronicity between the system clock signal and the reference clock signal. The system is resistant because it employs at least one of a lock-on unit and a synchronizing controller in operating the clock measuring circuit.
Abstract: A semiconductor integrated circuit system includes a first power line which supplies a first source power voltage, and a second power line which supplies a second source power voltage. A first edge detecting unit outputs a first edge detection signal when a rising edge of the first source power voltage is detected. A second edge detecting unit outputs a second edge detection signal when a rising edge of the second source power voltage is detected. An output unit is connected to the first power line, and outputs data to a data terminal in a data output cycle and sets the data terminal in a high-impedance state in response to the first edge detection signal. An output control unit is connected to the second power line, and controls the output unit in accordance with a read-data signal in the data output cycle, and controls the output unit in response to the second edge detection signal, so that the data terminal is set in the high-impedance state by the output unit.
Abstract: A method for producing a result prepared from asynchronous external events, wherein two mutually independent counting processes are activated, the temporal coincidence of the ends of counting of these two processes are verified and, on the basis of the information elements pertaining to the verification of each of these two counting processes and according to a specific sequencing of the application considered, a non-consolidated intermediate action is activated for each of the two sequencing processes and, after the verification of the temporal coincidence of the intermediate actions, and taking account of possible external priority actions, a resultant action is produced if all the necessary conditions are fulfilled.
November 29, 1996
Date of Patent:
February 16, 1999
Patrice Eudeline, Frank Gansmandel, Patrice Toillon
Abstract: A minimum value/maximum value extractor and method including: a multiplexer for outputting data and inverted data receiving from data lines depending on a maximum/minimum value selecting signal; a plurality of maximum value extracting parts for receiving the output of the multiplexer, a clock signal and a reset signal, the extracting parts outputting a first output which becomes the same signal state as that of the initially input data bits and maintains "0" regardless of subsequent data bits value once the input data bit becomes "0" until the reset signal is applied, and a second output which follows the first output value by delayed by two clock cycles; a maximum value/minimum value signal generator for outputting a value which is a NORed value of all inputs from the extracting parts as a minimum value or a value which is an inverted value of the NORed value of all inputs from the extracting parts as a maximum value; and a plurality of reset signal generators for generating the reset signal for resetting th
Abstract: A series delay generator for imposing a programmable delay on the timing edges of an incoming waveform is disclosed. The magnitude of the imposed delay is proportional to the value of a binary programming word. The series delay generator is implemented as a series of delay cells, each of which can be programmed into two delay states, a maximum delay and a minimum delay. The magnitude of the maximum and minimum delays can be set and calibrated using an analog tuning voltage. The series of delay cells can be segmentized in order to provide pipelined operation. The series delay generator is therefore capable of processing more than one timing edge at a time, permitting its minimum reprogramming time to span and even exceed the maximum delay span of the generator. A delay cell is also disclosed that uses a differential input and a digitally controlled current balance circuit to advance and retard the zero crossings of the incoming waveform and its inverse.
Abstract: A slew rate control circuit for an output circuit of an integrated circuit includes an input node for obtaining an input signal and an output node for providing an output signal. A first stage of the control circuit includes at least one transistor having a control terminal and first and second main terminals. The control terminals of each at least one transistor are connected together to the input node. The first main terminal of each at least one transistor are connected to a voltage rail. The second main terminal of each at least one transistor is connected to the output node through its own individual resistor. One or more subsequent stages of the control circuit each contain at least one transistor having a control terminal and first and second main terminals. The control terminals of each at least one transistor in each one or more subsequent stages of the control circuit are connected together to a control node driven from the control terminals of the preceding stage through at least one inverter.
Abstract: A semiconductor integrated circuit device includes a voltage drop circuit for generating a dropped voltage from a power supply voltage externally supplied to a power supply line, and a plurality of circuits respectively connected to the voltage drop circuit and driven by the dropped voltage. A switching unit, which is connected to at least one of the circuits, connects the power supply line to the above one of the circuits in synchronism with operation of the above one of the circuits. The above one of the circuits is driven by currents from both the voltage drop unit and the power supply line in synchronism with the operation thereof.