Abstract: A sheet counter has an elongate element (18) in which is formed a suction port (19), connected to a vacuum source by a duct (26). A pressure sensor is arranged to sense the pressure in the duct, in the vicinity of the port (19), and produces an electrical signal indicative thereof. The counter is set up by sensing the pressure in the duct with the port (19) open, either with the vacuum source operating or before operation thereof, and then by sensing the pressure in the duct with the port closed and the vacuum source operating. A pressure count-value part-way between the two sensed pressures is computed and during subsequent operation of the counter, a valid count signal is generated only if the instantaneous sensed pressure in the duct falls below the computed count-value.

Abstract: A synchronized voltage controlled oscillator lap counting circuit includes a bearing resolver circuit having a single Hall-effect sensor element which provides differential voltage output signals in response to an external magnetic field. The differential amplifier receives the differential voltage output signals and provides a single amplified output signal. The single amplified output signal is provided to a voltage controlled oscillator. A pedometer provides a repetitive pulsed-output signal in accordance with movements of a user. The repetitive pulsed-output signal and a voltage controlled oscillator output signal are provided to a micro-controller. The micro-controller samples the voltage controlled output signal in synchronization with the repetitive pulsed signal output from the pedometer to resolve bearing directions based on intercepted frequencies of the voltage controlled output signal.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.

Abstract: A frequency forming circuit according to the present invention utilizes division by a partial fraction a/b, and therein pulse removal means (2) first remove a-b pulses from the end of each consecutive period equal in length to a pulses. Thereafter, the pulse string is conducted to a digital delay line (4) consisting of serially connected, controllable elements (5) that produce essentially the same unit delay, and which includes an intermediate output before each element. Each pulse in said period is output from the delay line (4) before the element (5) whose ordinal number in the delay line is the same as the ordinal number of the pulse in said period. A multiplexer (7) receives the pulses from the intermediate outputs of the digital delay line and combines them to form a new pulse string. Control means (6) cause the control elements (5) of the digital delay line (4) to produce an average unit delay (a-b)*t/b with the same control.

Abstract: A method and apparatus for analyzing each microinstruction in a microinstruction-based electronic circuit having a plurality of registers to determine which registers in a processing cycle are not involved in the processing cycle, and preventing those registers from being clocked during such processing cycle. Hence, inactive registers during a processing cycle do not consume power at the level of active registers, thus lowering overall power usage by any system employing such gated-clock registers.

Abstract: In a semiconductor integrated circuit, a temperature sensor circuit includes a pulse source for generating a count pulse and a resistor having a resistance changing dependently upon a temperature change. The temperature detecting circuit is configured to convert the change of the resistance of the resistor responding to the temperature change, into the pulse number of the count pulses, in response to each application of a temperature measuring signal having a first frequency, in order to generate a count signal. A counter counts the count signal and accumulates a count value for each temperature measuring signal so as to hold the accumulated count value. The counter outputs the accumulated count value in response to a reset signal having a second frequency lower than the first frequency. The counter is then reset by the reset signal.

Abstract: The invention provides a high speed variable rate output pulse generating circuit for a semiconductor testing device. The circuit includes a shift register formed of 2n number of flip-flops which counts the lower bits of lower counter data selected by a selector, a ripple down counter formed of m number of flip-flops counts the upper bits of upper counter data selected by a NOR gate. A counting end judgment circuit for judging an end of counting the ripple down counter and the shift register produces a counting end signal. A first flip-flop latches the counting end signal to supply a counter load signal to the selector and the NOR gate to load subsequent data, and a second flip-flop generates a first output clock pulse.

Abstract: There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: The integrated circuit with programmable pad driver involves an integrated circuit (IS1) with at least one pad driver that has a programming unit (PE) and a plurality of sub-drivers (T1 . . . Tm). A specific driver intensity and edge steepness of the pad driver can be set in that a corresponding plurality of sub-drivers connected to a common terminal contact (PAD) at their output side are activated/deactivated dependent on output signals (P1 . . . Pm) of the programming unit.

Abstract: A deviation of a clock rate of the timepiece clock signal is determined relative to a reference clock rate of a reference clock signal (CR) which is either issued while the mobile unit is switched on or is contained in a received signal. The reference clock rate is higher than the clock rate of the timepiece clock signal. A count number (N) is calculated based on the deviation of the clock rate of the timepiece clock signal. The clock signal is generated such that the clock pulses the clock signal are successively issued each time the clock pulses of the timepiece clock signal counted up to the count number.

Abstract: There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption.An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition.

Abstract: The present invention relates to a procedure for counting faintly luminescent particles, and relates specifically to a procedure for counting cells and microorganisms marked with a colored or fluorescent stain or marker that selectively marks the microorganisms and cells to be counted, characterized by the fact that the said procedure is implemented with the aid of a photon-accumulator camera and includes the acquisition of at least one low-resolution image I, the threshold processing of the said low-resolution image in order to obtain at least one digital image Ib, at least one dimensional filtration stage, and the counting of the number N of objects belonging to a given class of sizes in the digital image Ib.

Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data put signal. The first and second input latches have first and second shutoff circuits, respectively. During a precharge phase, the first and second input latches each provide an output signal of a first logic level. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal, respectively. In response to the samples of true and the complement of the data input signal, one input latch's output signal will transition to a second logic level, while the other input latch's output signal will remain at the first logic level. A first output latch and a second output latch are coupled to receive the output signals of the first and second input latches, respectively. The first and second output latches are inverting.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A delay locked loop, temperature independent, wide range frequency clock multiplier that outputs a clock signal that has a frequency that is a multiple of the frequency of the input clock signal. The multiplier does not use any phase-locked circuitry. It has adjustable delay lines or cells that are cascaded and have outputs to a multiple input exclusive OR gate. The exclusive OR gate outputs the multiplied frequency signal. A delay controller outputs a signal to each of the delay lines or cells for setting the amount of delay in each line or cell. A delay monitor has inputs from the exclusive OR gate output and the delay controller output. The delay monitor outputs signals to the delay controller which has a phase differentiator. The delay controller output is such to maintain a particular duty cycle on the waveform of the multiplied frequency signal output from the exclusive OR gate.

Abstract: A high speed barrel shifter in which fill input data is especially added.

Abstract: A high-speed counter circuit comprising an input line for inputting a clock signal, at least two bit counters for generating a count value of at least two bits in response to the clock signal from the input line, at least one clock synchronizing circuit responsive to an output signal from at least one higher-order bit counter of the at least two bit counters, for transferring the clock signal from the input line to a lower-order bit counter of the at least two bit counters, and a delay circuit for delaying the clock signal from the input line by a propagation delay time of the at least one clock synchronizing circuit and applying the delayed clock signal to a highest-order bit counter of the at least two bit counters. According to the present invention, the high-speed counter circuit can minimize a delay time from the application of the clock signal to the generation of the count value to enhance the operation speed.

Abstract: The present invention provides an output buffer having a self back-bias compensating circuit that adapts the effective output transistor size to overcome current-reducing threshold voltage shifts caused by connection of the output n-wells to a high voltage. More particularly, this invention provides a circuit configuration in which bias level detection is used to switch in additional PFET legs under high back bias conditions. The extra driver legs are disabled under zero back bias. This compensates for the effect that different voltage switching environments have on PFET performance.