Abstract: The present invention provides power saving features that can be used in a computer or other device employing an internal clock to dynamically change the frequency at which the clock operates to respond to demands upon system resources. For example, the CPU clock in the synchronous logic core may be changed dynamically to reduce power consumption without causing a CPU lock-up. A PLL clock internal to the CPU has a reduced sensitivity to external clock changes. The present invention provides a means to incrementally change the internal clock frequency by intermittently stopping the output of the internal clock.

Abstract: A large number of frequent events may be accurately counted by employing a shift register. The values of several bit positions within the shift register are logically combined to generate an input to the shift register. The input is shifted in to alter the register contents whenever an event to be counted occurs. The bit positions for generating the input are selected to produce the longest sequence of nonrepeating patterns possible. The event counter may be implemented in a small area, allowing a large number of event counters to be implemented in an array like structure within a single device and to operate as extremely high frequencies.

Abstract: A unified bi-directional LFSR is fabricated from latches having dual (Forward and Reverse) inputs. Each such latch accepts its inputs upon receipt of a clock signal that is respectively associated with the forward or reverse direction. The appropriate collection of XOR gates exists between latch outputs and the inputs associated with a forward clock signal, so as to produce the forward sequence. Likewise, another appropriate collection of XOR gates exists between the latch outputs and the inputs associated with the reverse clock signal. To produce a "reverse" LFSR corresponding to the polynomial that is the reciprocal of the polynomial for the "forward" LFSR, the latches of the reciprocal (reverse direction) LFSR are construed as being numbered in the opposite order. That is, a single set of latches (register) has both a forward linear feedback network and a reverse linear feedback network.

Abstract: A protection circuit for at least one power transistor which has at least one control terminal and two main conduction terminals defining a main conduction path includes a first detection means designed to generate a first electrical signal approximately proportional to current flowing in the main conduction path. Second detection means are designed to generate a second electrical signal approximately proportional to voltage across the main conduction path. Multiplying means receive at input the first and second signals and are designed to generate an electrical product signal substantially corresponding to the product of at least the latter. A generator generates an electrical reference signal, and operational amplifier means receive at input the product signal and the reference signal and are designed to generate an electrical difference signal substantially corresponding to their difference.

Abstract: A feedback and shift unit is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a particular operating function, such as a linear feedback shift or a stepping function used by encryption algorithms. The feedback and shift unit (50) comprises a linear feedback shift register (52) for storing a value of the feedback and shift unit. A tap register (56) stores a tap position indicator indicative of tap positions for the feedback and shift unit (50). An input provides data to the feedback and shift unit. A feedback matrix, coupled to receive the data from the input, provides data bits, generated in response to the data and the tap position indicator, that are shifted into the linear feedback shift register (52) to form the value stored therein.

Abstract: A master-slave-master latch circuit for loading data vertically or horizontally. A first master latch is coupled to an input terminal for receiving data. Under control of a clock, the data is transferred from the master latch to a slave latch input terminal. Under control of the slave latch clock, the data is shifted horizontally into the slave latch. Under control of a further horizontal shift clock the data is shifted to a further master latch. The slave circuits are organized in a vertical column fashion so that data may be shifted vertically up or down the slave latches as provided from the master latch. Feedback circuits from the master latch to various positions within the slave latch column permit the data to be selectively transferred from one horizontal level to the prior horizontal level for placing in the vertical column.

Abstract: In an ATD circuit, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means generates a first output signal having a first pulse width in response to a change in external address signal and generates, when the external address signal becomes a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means receives therein the signal generated by the pulse width amplifier circuit and waveform-shapes the output signal so as to provide an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal generated by the first circuit means.

Abstract: A method for the resetting of a group of series-connected non-transparent synchronous memory cells. The method includes modifying the clock signals that control the transfer gates of these cells on the activation of a resetting signal to set all the transfer gates in the on state. The method is particularly suited to the resetting of long shift registers such as those used in cryptographic applications, especially in micro-circuit cards, and the reset circuitry can be implemented using conventional logic gates.

Abstract: Independent functional units are clocked by a clock source generator having at least two adjustable delay lines for independently adjusting the duty cycles of at least two clocks so that speed path margins are individually optimized for each functional unit.

Abstract: A machine for counting discrete articles, such as tablets, pills, or capsules, comprising a feeder including a hopper for receiving and dispersing a plurality of tablets to be counted into separate streams, a plurality of detectors associated with each stream for detecting each tablet in that stream, a counter coupled to said plurality of counters for counting the total number of tablets in all of the streams and a switching device coupled to each of said plurality of detectors for preventing detector saturation and delay, thereby improving counter accuracy and speed.

Abstract: A high-speed rotator array for shifting input data a specified amount. The rotator array includes a plurality of straight shift control lines extending across the array for receiving shift data representative of shift values, and a plurality of input terminals for receiving input data to be shifted. The rotator array also includes a plurality of data lines coupled to the plurality of input terminals that extend both diagonally and horizontally across the array. In response to the rotator array receiving the shift data and the input data, a plurality of output terminals transmit the shifted output data.

Abstract: According to the present invention, the invention relates to a semiconductor device having an activity monitor circuit formed thereon for monitoring the switching activity of signals generated by other circuits on the device during burn-in testing. In one embodiment, the activity monitor circuit includes means for detecting a present state of a signal; means for comparing the present state with a previous state of the signal; means for determining whether the state of the signal has switched a requisite number of times in a predetermined time period; and means for displaying the results of the determination.

Abstract: An object counter includes a feeding funnel having a frustroconical section, the narrow end of which is coupled to a substantially vertical feeding channel having a substantially rectangular cross section. A pair of linear optical sensor arrays are arranged along adjacent orthogonal sides of the feeding channel and a corresponding pair of collimated light sources are arranged along the opposite adjacent sides of the feeding channel such that each sensor in each array receives light the corresponding light source. Objects which are placed in the feeding funnel fall into the feeding channel and cast shadows on sensors in the arrays as they pass through the feeding channel. Outputs from each of the two linear optical arrays are processed separately, preferably according to various conservative criteria, and two object counts are thereby obtained. The higher of the two conservative counts is accepted as the accurate count and is displayed on a numeric display.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying application of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.

Abstract: The present invention provides a delay clock generator where a plurality of stable delay clocks can be generated and digitizing is easy. The delay clock generator comprises first to nth (n: integer not less than 2) delay circuits (11 to 1n) connected in cascade connection for delaying the basic clock (KO) in sequence, a phase comparator (21) for comparing phase of a delay clock from the nth delay circuit (1n) with that of the basic clock, and a delay control circuit (31) for generating a delay control value to make the phase of the delay clock from the nth delay circuit synchronize with that of the basic clock based on a phase comparison result, and for controlling delay amounts of the first to nth delay circuits respectively by the delay control value.

Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Abstract: A semiconductor integrated circuit to determine a passage of time that may include a time during which no electrical power is supplied to the circuit is disclosed. The circuit has a timing device that includes a memory storage dielectric material for trapping charge carriers and releasing the trapped charge carriers in a known manner over time. The timing device has an electrical parameter that is relatable to an electric field created by the trapped charge carriers. A charge injection circuit is provided for selectively injecting charge carriers into the memory storage dielectric material to create an initialized state, and a time reader circuit determines when the electrical parameter has reached a predetermined value that corresponds to a passage of a predetermined time. Preferably the timing device is an insulated gate field effect transistor in which the memory storage dielectric material is a dielectric material, such as SONOS or SNOS, between the gate and channel overlying at least the channel area.

Abstract: A shifting circuit operates on a plurality of input sub-words, that collectively constitute an input data word, to generate a plurality of result sub-words that collectively represent the input data word, shifted. The shifting circuit receives, during each cycle, a separate one of the plurality of input sub-words. A combiner/selector performs a shift on each sub-word provided on the I-bus, taking carry-in bits from a carry-in register. Before a shifting operation is executed, the carry-in register is initialized to zero. (Alternately, the carry-in register may be reset to zero after a shifting operation is executed.) The carry-in register is also connected to receive the sub-words provided by the data source circuit onto the I-bus.

Abstract: A method of automatically determining the number of filaments making up a synthetic yarn, or other yarn such as staple natural fibers comprising removing a small cross-section of the yarn to create a plurality of small filament pieces, and automatically counting the small filament pieces to determine the number of filaments in the yarn.

Abstract: A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.