Abstract: An integrated circuit and method produce a first clock signal (CLOCK) from a reference clock (REFCLK) but at a different frequency. A variable delay line (32) produces the first clock signal by introducing a variable delay in the reference clock signal that is controlled by a programming signal generated in a counter (34). The programming signal is incremented by a second clock signal (UP) while transitions of a fixed delay clock signal lead transitions of the first clock signal. When the programming signal reaches the count of a rollover code (ROLLOVER), the programming signal is reset to a zero count to begin a new sequence. A calibration circuit (36, 38, 40, 42) determines the count of the programming signal needed to produce the rollover code when the variable delay is at least as great as one period of the reference clock signal.

Abstract: A clock generates clock pulses defining a plurality of clock cycles. A circuit is connected to receive the clock pulses and measure a primary time of occurrence of an event with respect to a clock cycle. Logic circuits are provided to generate a timing pulse representing a time interval between the event and a clock pulse of the subsequent clock cycle. The timing pulse begins at the time of the event and ends on the occurrence of a subsequent clock pulse. A filter circuit receives the timing pulse and generates in response thereto a signal having an amplitude representing the duration of the timing pulse. The amplitude is measured to determine the width of the timing pulse thereby identifying the occurrence of the event with respect to a subsequently occurring clock pulse.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: A circuit for synchronizing a periodic ramp signal utilized in a switching mode power converter to system clock signal. A capacitor is charged through a resistor. When a voltage across the capacitor reaches a predetermined level, the capacitor is discharged and the charging cycle is repeated, thereby generating the periodic ramp signal across the capacitor. A waveform shaping circuit shapes the ramp signal into a rectangular wave signal having a same frequency and phase as the ramp signal. A phase comparator compares a phase of the rectangular wave signal to a phase of the system clock signal for forming a phase error signal. The phase error signal controls a level of current supplied to the timing capacitor by a voltage controlled current source. When the frequency of the system clock signal is higher than the frequency of the ramp signal, the phase comparator causes the voltage controlled current source to supply additional current to the capacitor, increasing the frequency of the ramp signal.

Abstract: A pulse detecting system 1 has a high speed A/D converter 10 and a slew controlled pulse detector 110. The A/D converter 10 has large hysteresis for holding the converted digital value of an input signal V.sub.PULSE until the A/D converter 10 is reset. The slew controlled pulse detector 110 limits the slew rate of large amplitude pulse to correct arrival errors and provide an output signal V.sub.AT that more accurately represents the arrival time of the input pulse signal, V.sub.PULSE.

Abstract: The present invention provides a method of and an apparatus for producing an output signal which is, relative to a periodic input signal, delayed by a predetermined phase angle phi. Initially, the phase angle phi between 0 and 2.pi. is divided by 2.pi. and multiplied by a predetermined positive integer number Z, whereby an integer phase number F between 0 and Z in obtained after rounding. Then, timing-pulse are, beginning with zero, counted between a first and a second input pulse, and an integer relative phase number P is obtained from the number N of the timing-pulses by multiplying by the phase number F, dividing by Z and rounding. Following the second input signal, the timing pulses are, beginning with zero, counted until the relative phase number P in reached. At last, an output pulse is emitted upon reaching the relative phase number P.

Abstract: A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a "buffer" and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

Abstract: A rational frequency division device eliminates spurious components by a simple arrangement and can set a broad frequency modulation range. A frequency synthesizer using the rational frequency division device includes an arithmetic circuit, which outputs the frequency division ratio to a frequency divider in a PLL circuit constituted by a variable frequency oscillator 4, a frequency divider 6, and a phase detector 2. The arithmetic circuit includes a plurality of series-connected cumulative adders 22 which include a first cumulative adder that receives a rational number defined by an integer value and a decimal value, an integer value extraction circuit 23 for extracting an integer value from the output value of the cumulative adder of the final stage, and a delay circuit 24 for outputting the integer value extracted by the integer value extraction circuit to the frequency divider as the frequency division ratio, and outputting the integer value to the respective cumulative adders as a feedback value.

Abstract: An apparatus for controlling an electrical appliance coupled with an output terminus and configured to operate in response to an alternating input signal, such as input AC power. The apparatus comprises a reference signal generator for receiving the input signal and generating a reference signal (either V.sub.RAMP or V.sub.CONTROL) in response to the input signal, and a control circuit for controlling connection of the input signal to the output terminus in response to the reference signal and to a user-defined set-point signal. The control circuit is coupled with the reference signal generator and with a set-point terminal. The set-point terminal receives the set-point signal and the control circuit controls connection of the input signal with the output terminus in response to a predetermined relationship between the reference signal and the set-point signal; the apparatus is capable of generating a modified periodically interrupted AC power output based on an AC power input.

Abstract: In a level shifted high voltage MOSgate device driver which drives MOSgate devices such as IGBTs and power MOSFETs, effects of negative voltage swings caused by currents commutating through L.sub.S1 and L.sub.S2 inductances in the power circuits are avoided due to several measures. First, the values of the inductances L.sub.S1 and L.sub.S2 are reduced by keeping short conductor lengths, by other layout/wire bonding techniques to reduce the values of the L.sub.S1 and L.sub.S2 inductances. The external, charging capacitor C.sub.b value is increased substantially to reduce the voltage buildup on the internal circuitry. A typical value is 0.47 .mu.F, for a given circuit, IGBT and layout combination. The size of the C.sub.VCC capacitor is selected to keep the supply voltage as stiff as possible. Preferably, C.sub.VCC is at about ten times the value of the sum of the C.sub.b capacitance in the circuit. The resistance R.sub.b in the bootstrap path is reduced as much as possible, preferably to zero.

Abstract: A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter that starts counting when transmission by either the port it is associated with is transferring a cell, or when another port is transferring a cell on a channel that conflicts with the channel attached to the port. The counter counts the appropriate number of digits corresponding to the length of the cell whereupon the port is provided with a signal indicating that the transmission has ended. In association with other control signals, the port may then begin transmitting a new cell. When multiple switches are attached to the same channel, the counter serves as a self-queuing mechanism that relieves a central controller from having to keep track of the transmission of bits by each port, and from having to select the next port for transmission.

Abstract: A high speed differential data latch includes identical master and slave flip-flops. The master flip-flop is driven by a differential input data signal while both flip-flops are driven by a shared differential clock signal. Each flip-flop includes: one differential amplifier for sequentially latching the differential input data signal to provide a differential output data signal; a second differential amplifier for generating two switched supply currents from the clock signal for powering the differential data amplifier; and a third differential amplifier cross-coupled to the differential data amplifier for providing positive feedback thereto for enhancing the latching speed. The differential output data signal follows the differential input data signal during one of the differential clock states and remains latched during the other differential clock state.

Abstract: A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.

Abstract: A system for determining the time between the receipt of two different sils, includes a voltage ramp generator which generates a time dependent voltage signal upon receipt of a timing pulse at a time T.sub.1, and provides the instantaneous value of the voltage signal when the voltage ramp generator receives an input signal having a predetermined threshold value at time T.sub.2. A data processor coupled to receive the voltage signal, generates the timing pulse, and determines a time difference .DELTA.T from the voltage signal, where .DELTA.T=T.sub.2 -T.sub.1.

Abstract: A high-speed predecoding address counter circuit comprising at least three tetrad counters connected in series, each for inputting an external 4-bit address decoding signal in response to a set signal and cyclically shifting a logic signal with a specific logic value at its four output terminals in response to a clock signal, a first clock switching unit responsive to a logical value of a most significant bit of an output signal from a lowest-order one of the at least three tetrad counters, for transferring the clock signal to a higher-order one of at least three tetrad counters, at least one logic unit for detecting whether both most significant bits of output signals from at least two lower-order ones of the at least three tetrad counters have the specific logic value, and at least one second clock switching unit connected between at least one logic unit and at least one of the at least three tetrad counters other than the at least two lower-order tetrad counters, for switching the clock signal to the at le

Abstract: A rotor assembly for counting sheets in a stack has a support on which is rotatably mounted a rotor such that the rotor engages an edge region of the stack. The rotor has a plurality of helical transfer grooves through which sheets are transferred one at a time from one side of the rotor to the other. A foot bears on the rotor and has a port which, as the rotor rotates, comes into and out of communication with further ports on the rotor each leading to a respective groove, whereby air is drawn in a timed relationship through the rotor to assist the transfer of sheets through the helical grooves. The rotor is movable axially with respect to its support and there is a detector arranged to detect the position of the foot with respect to the support thereby to give an output indicative of the position of the rotor with respect to the support.

Abstract: A frequency departure detecting circuit permits flexibly modify a detecting condition of frequency departure. A working reference clock is counted for a given period. On the basis of uniformity between bits of given number of upper bits of the counted value, large magnitude of frequency departure of repeated frequency of the reference clock from a frequency that should be is judged. Also, through comparison of given number of lower bits of the counted value and externally set detecting value, departure of the repeated frequency of the reference clock from the frequency that should be, is judged. When the counted value reaches a predetermined value, free running condition of the counter is judged to stop counting operation. When judgement is made that the repeated frequency of the reference clock is departed from the frequency that should be, the working reference clock is replaced with a back-up reference clock in response to an alarm.

Abstract: An integrator circuit is disclosed which overcomes problems in the art described above. In accordance with the present invention, an integrator circuit includes a differential input transconductance stage which converts an input differential signal to a differential current at first and second internal nodes. These two internal nodes are buffered from an integrating capacitor by two pass transistors, the conductance of which is automatically adjusted in response to the voltage at the two nodes. In this manner, the first and second nodes act as nearly ideal current sources. Thus, the integrating capacitor sees a nearly infinite impedance, thereby allowing the integrator circuit to achieve a large RC time constant while employing relatively small internal resistances. Further, the integrator circuit is fully differential and includes a floating capacitor having equal leakages on each of its plates. Being responsive only to differential signals, the integrator circuit thus ignores common mode leakages.

Abstract: To evaluate cleanliness of wafer accommodating members used for storing or transporting of silicon, gallium arsenide or like semiconductor wafers, pure water is poured into a vessel-like wafer accommodating member, such as a wafer case body, a top cover, etc., capable of containing liquid therein, and then low frequency vibrations or supersonic wave is applied to the member. Alternatively, inner wafer accommodating members accommodated in the wafer case body, such as a wafer basket, a wafer retainer, etc., are accommodated in a vessel containing poured pure water, and the low frequency vibrations or supersonic wave is applied to the members. Then, the quantity of particles in the water is counted. Particles that have been attached to the wafer case or to inner wafer accommodating members accommodated therein, such as a wafer basket, a wafer retainer, etc., are made readily separable into the water, thus permitting quantitative detection of generation of particles from the inner wafer accommodating members.

Abstract: A method for detecting the position of a linear stepping motor which includes the steps of generating a reference clock signal for detecting the position of the linear stepping motor using an oscillator and counting the reference clock signal with a counter, generating digital values of carrier sine waves sin.omega.t and cos.omega.t by inputting the output of the counter to a ROM having sine and cosine functions, converting the digital values of the carrier sine waves sin.omega.t and cos.omega.t to analog sine wave signals sin.omega.t and cos.omega.t using a digital-to-analog converter and outputting the result, generating the signals sin.omega.tcos.theta. and cos.omega.tsin.theta. by multiplying the analog sine wave signals sin.omega.t and cos.omega.t by sine wave signals sin.theta. and cos.theta. from a linear scale in a multiplier, adding the signals sin.omega.tcos.theta. and cos.omega.tsin.theta. in an adder to form a modulated signal sin(.omega.t+.theta.), converting the a modulated signal sin(.omega.t+.