Abstract: In a data communication system, apparatus provides a clock signal having a frequency of twice the frequency of a first clock signal. A time delay circuit delays the first clock signal by a time delay to provide a delayed first clock signal. An exclusive OR circuit is coupled to the first clock signal and the delayed first clock signal. The output of the exclusive OR is a second clock signal having a frequency twice the frequency of the first clock signal.
Abstract: A method and structure for performing data synchronization by delaying the input data for substantially one-half of the VCO signal period and then comparing the phase of the delayed input data to the VCO signal. The phase difference is filtered and controls the frequency of the VCO signal to align the VCO signal with the delayed input data. The delayed input data is clocked into a flip-flop on the opposite phase of the VCO signal to produce an output signal. In a preferred embodiment the delay of the input data for phase comparison, and the delay of the input data for the output flip-flop can be independently selected.
Abstract: An arrangement for monitoring slip in a digital transmission system. A PRBS sequence is transmitted in one channel or timeslot of the system. At a receiving station a characteristic group of N bits of the received sequence is assembled. The assembled group is compared with locally formed groups of N bits which would be expected to occur if a slip has occurred.
Abstract: An equalizer for equalizing an input data signal of a digital transmission filter for jitter, overshoot and undershoot in amplitude includes a delay circuit which delays an input non-return-to-zero (NRZ) data signal a specified number of bits by synchronizing the input data signal with a basic clock signal, and outputs a plurality of delayed data bit streams each corresponding to a respective delay element of the delay circuit. The delayed data bit streams are input to a logic circuit which produces a plurality of voltage control signals corresponding to patterns of logic symbols in the data bit streams of the delayed input data signal, these voltage control signals designating information as to how much the delayed input data signal will be distorted due to data signals adjacent thereto upon passing through a digital transmission filter.
Abstract: Apparatus and method are disclosed for implementing a clock and data recovery circuit for use on digital networks. A fully integrated phase-locked loop extracts a clock signal embedded in a data stream. Two trimming digital-to-analog converters simultaneously bring the center frequency of a current controlled oscillator and the phase-locked loop closed loop bandwidth to desired values. A triple sampler captures jittering data and aligns them with the recovered clock. The input jitter tolerance for the method and apparatus is two to three times that of previously reported phase-locked loop based circuits.
Abstract: A DS1 dejitter circuit has a control circuit for generating six pulses over a one hundred and ninety three 1.544 Mb/sec clock cycle, and a clock circuit for tracking the frequency of a jittered incoming DS1 signal, and based on that frequency, and utilizing the six pulses, generating a clean DS1 signal at the nominal rate of the jittered incoming signal. The control circuit preferably includes a divide by 28 or 29 circuit which receives a 44.736 Mb/sec (DS3) input clock signal, a mod 193 counter, and a count decoder for providing the six control pulses over the 193 count. Logic circuitry is provided for taking the outputs from the count decode and controlling the divide block to guarantee that the divide block divides the DS3 signal by 29 one hundred eighty-eight times for every five times the divide block divides the DS3 signal by 28. In this manner an average clock of 1.544 Mb/sec (the standard DS1) rate is obtained from the divide block.
Abstract: The frequency of a clock for a receiving terminal is controlled based on a predetermined clock frequency of a terminal that produces a continuous stream of data at a predetermined frequency for transmission to the receiving terminal over a communications network of the kind in which data is transmitted between the terminals in discrete packets that are delayed on the network by possibly different amounts. Arrivals of packets that are sent to the receiving terminal are detected, time intervals between the arrivals of the successive packets are determined, and the time intervals are processed to generate an estimate that is related to the predetermined frequency. The frequency of the receiving terminal clock is controlled in response to the estimate. In one aspect, the time intervals are determined by measuring time differences of arrival between successive packets, and the measured time differences are filtered to generate the estimate.
Abstract: A method and apparatus for recovering a clock signal from a random NRZ data signal is shown to include a phase detector for detecting the phase difference between the random NRZ data signal and a clock signal and for generating a phase signal representative of the phase difference. The phase signal is a binary signal having first and second logic levels, wherein the first logic level is representative of the clock signal having an early phase relationship with the data signal and wherein the second logic level is representative of the clock signal having a late phase relationship with the data signal. Clock recovery also incorporates an integrator for integrating the phase signal over a period of time and for generating an integration signal representative of such integration and an oscillator for generating the clock signal at a clock frequency responsive to both the phase signal and the integration signal. The clock frequency is determined by a centering factor and an offset factor.
Abstract: A phase-adjusting circuit for adjusting the phase relation between an input data string supplied via input lines includes sync detecting apparatus provided for each of the lines for generating frame sync-detection signals by detecting frame sync signals of the input data strings. Apparatus is provided for detecting a first data string having a largest delay of the input data strings. A phase difference-detecting apparatus detects phase differences between the first and the remaining data strings to produce phase difference signals for such remaining data strings. A line connecting signal-generating apparatus is responsive to the phase difference signal for generating line connecting signals. A variable-delay apparatus is responsive to the phase difference signals for outputting delayed data strings by giving delays to the remaining data strings.
Abstract: A decoding signal processing mechanism preserves the use of a single high data rate encoder at a transmitter site, so that the input data may be continuously encoded and transmitted, while using multiple low data rate decoders at the receiver site in such a manner that "end effects" are avoided and the performance of high data rate decoding is attained. At the transmitter site, digital information signals are encoded at a first encoding rate and then transmitted over a communication channel to a receiver site. At the receiver site signals to be decoded are coupled to a respective one of a plurality of decoders which decode, at a second rate less than said first, encoding rate, respective overlapping blocks of received encoded digital information signals and derive respective portions of the digital information signals. The decoded outputs of the decoders are combined to recover the digital information signals.
Abstract: A clock recovery circuit serves to recover a clock signal from data which does not arrive at predetermined times and which may be bursty. The clock recovery circuit operates in conjunction with a buffer which receives the data. Illustratively, the clock recovery circuit maintains a first count of the bytes of data written into the buffer and a second count of the byte of data transferred from the buffer. A subtractor substracts the second count from the first and a decision circuit utilizes the result to provide a signal indicative of the current occupancy of the buffer. Depending on the current occupancy, the frequency of an output signal of the clock recovery circuit is increased, decreased, or maintained as constant. This output signal thus serves as the recovered clock signal.
Abstract: The invention provides a receiving counter phase synchronization circuit of the synchronous transmission system, the circuit comprising first line transmitting the signals of logic status according to whether or not synchronization pattern is detected in the serial bit stream; second line transmitting the pre-existence phase information of the receiving counter; a D flip-flop circuit for outputting the delayed data under the control of a clock signal; first NOR logic device connected to the output line of said D flip-flop circuit and said second line; second NOR logic device connected to said first NOR logic and said first line, and having its output line connected to said the data input node of said D flip-flop circuit; an inverter connected to said first line; and an OR logic device connected to the output line of said inverter and that of said first NOR logic device.
December 11, 1989
Date of Patent:
March 26, 1991
Electronics and Telecommunication Research Institute, Korea Telecommunication Authority
Abstract: A synchronizing buffer which synchronizes data link data with the channel clock such that one character is transmitted onto the data link for each channel clock. The synchronizing buffer disclosed includes a first-in-first-out (FIFO) buffer which receives data characters from a data channel buffer, and outputs them onto the data link. When the channel clock is stopped, the synchronizing buffer circuit places idle characters on the data link with the proper disparity. When the channel clock restarts, the circuit synchronizes the sending of restarted data characters with the idle characters placed onto the link such that there is an intelligible string of characters on the data link at all times.
October 30, 1989
Date of Patent:
March 26, 1991
International Business Machines Corporation
Abstract: A process for receiving a binary digital signal by a method for the reception of a binary digital signal, which may also have phase shifts, with a supplied clock that may have any desired phase position with respect to the digital signal and may deviate somewhat in frequency from the bit sequence frequency of the digital signal. From the clock (T1) there is formed over a delay chain (7-13, 52-55) a series of clocks (T2-T12), which have approximately equal phase intervals. Short pulses (I11-I110) are derived from the clocks (T1-T12). T12). Upon the arrival of each edge of a digital signal (D1) that has been selected as the effective edge, there is derived a read pulse (I21) which may also be delayed (I2x), with which the presence of pulses (I11-I110) may be determined through AND gates (20-25, 60-63). Through SR flip-flops (26-31, 64-67) and AND gates (32-37, 68-71), clocks (F1-F10) selected with the pulses (I11-I110) that are present are switched through and OR-linked (38) for use as an input clock (Te).
Abstract: A method and apparatus for determining the phase and amplitude accuracy of continuous-phase-modulated signals is described. A modulated RF signal generated by a transmitter is down converted to a relatively low intermediate frequency which is filtered and sampled by a high sampling rate analog-to-digital convertor. A digital signal processor processes the digital signals to produce a measured amplitude function and a measured phase function corresponding to the modulated RF signal. From the measured amplitude and phase functions, an ideal phase function corresponding to the modulated RF signal is calculated and synthesized. The ideal phase function is compared to the measured phase function to determine the phase function from which the modulated RF signal phase error and frequency error are computed.
January 13, 1989
Date of Patent:
March 19, 1991
Raymond A. Birgenheier, Richard P. Ryan
Abstract: A method and an apparatus for demodulating M-ary PSK signals of the type wherein the modulation is limited to phase transitions between adjacent phase states. The method is operative in a demodulator which comprises a phase splitter dividing a source signal into two paths with a preselected phase relationship among phases, one of the phases being delayed by nominally one bit period, a mixer or multiplier receiving as one input a representation of the delayed-phase component and as a second input a representation of the other phase component. A signal is filtered by a lowpass filter and provided to at least one corresponding two-level comparator, each of which produces a digital output. Digital logic circuitry responds to the digital outputs of each of the comparators to map the digital outputs into a single digital bit stream of ones and zeros.
Abstract: A decision feedback equalizer includes a transversal feedforward digital filter section (16) and a recursive feedback digital filter section (18) including a decision stage (20). In order to optimize the performance of the equalizer, the reference tap position is preferably aligned with a storage location of the feedforward filter section (16) containing the first sample of a current symbol and any contemporaneous samples of preceding symbols, the second and subsequent samples of the current symbol being contained in other storage locations of the feedforward filter section (16). In the case of data being in bursts a better performance may be obtained by time reversing the data applied to the feedforward filter section (16).
Abstract: A multi-channel trellis encoder/decoder is disclosed for use with multi-channel data transmission systems. For each data transmission symbol interval, trellis encoding is applied across all available channels, and for each data reception symbol interval trellis decoding is applied across all available channels. In comparision with systems employing independent trellis encoding along each available channel, the present invention reduces data throughput delays by roughly an order of magnitude, and reduces implementation complexity by roughly a factor equal to the number of transmission channels. Further, the multi-channel trellis encoder will permit different data transmission rates as well as permitting variations in signal power and/or noise power from channel to channel.
August 12, 1988
Date of Patent:
December 25, 1990
Dwight W. Decker, Gary A. Anwyl, Mark D. Dankberg, Mark J. Miller, Stephen R. Hart, Kristi A. Jaska
Abstract: In a receiver comprising a filter section for filtering a transmitted digital signal into a filtered digital signal and an equalizer section for equalizing the filtered digital signal into an equalized digital signal as a reproduced digital signal in response to controllable tap gains supplied from a control arrangement, the equalizer section comprises a first arrangement for filtering the filtered digital signal in response to predetermined ones of the controllable tap gains to produce an intermediate digital signal and a second arrangement for equalizing the intermediate digital signal into the equalized digital signal in response to remaining ones of the controllable tap gains except for the predetermined controllable tap gains to produce the reproduced digital signal.
Abstract: A method and arrangement for generating a correction signal for a digital clock recovery circuit. This method cost effectively provides phase sensors that can be realized in integrated technology. In a sample-and-hold circuit, an auxiliary data clock (DHT1) that is valid as a recovered clock of a digital signal (DS1) and whose clock frequency is somewhat higher or lower than the bit rate of this digital signal (DS1) is sampled by the latter. Then a trailing edge of a pulse of this auxiliary data clock (DHT1) is identified by a status change. The sample-and-hold circuit then outputs a correction request signal (K1) that releases a correction signal (K) in a following circuit, this correction signal (K) being synchronous with the auxiliary data clock (DHT1). This method is utilized in digital clock recovery equipment.