Abstract: The circuitry of the present invention taps a DS0 data stream and outputs a timing signal to drive terminal multiplexers. Even if the data bit stream is lost, the present invention continues to provide proper clocking signals. A composite clock (bit and byte clock) is provided by the present invention with the bit clock at 64 KHz and the byte clock at 8 KHz in the preferred embodiment. To avoid the problem of phase shift over long distances (limiting cable length) the present invention phase adjusts the digital bit stream clocking signal with a 360 degree delay, giving the appearance of advancing the signal in phase. An additional delay of one frame width is applied to the signal. A negative phase delay equivalent to cable runs from 0-1500 feet in 500 foot increments is also applied. In the preferred embodiment, a shift register is tapped in reverse order to accomplish this phase delay.

Abstract: Method for receiving carrier oscillations modulated with a useful signal. For a universal transmitting/receiving device, a method for the automatic adaptation of its modem to the type of modulation of the incoming signal is provided in which the incoming DPSK signal is first demodulated. The demodulator output signal is then converted into a polar co-ordinate representation and, after formation of the difference phase angle (.DELTA..phi.), its value frequency (H) is represented modulo 90.degree. in a histogram which can be evaluated for derivation of the control information.

Abstract: Disclosed is a tracking bit synchronizer for use in digital data apparatus such as high density digital magnetic tape recorders. The disclosed bit synchronizer effects synchronization of data if the data rate is known within one octave. Moreover, data rates can change during operation over an octave range without bit errors or other loss of data. The bit synchronizer includes a phase locked loop which produces a clocking signal in synchronism with incoming encoded data. A data error detector uses information from a data decoder to determine if phase lock at the proper data rate has occurred. Control circuitry uses this information, along with the output voltage of the phase locked loop filter, to operate the phase locked loop in either a seek mode or a tracking mode. A squelch circuit prevents phase corrections during data signal dropouts.

Abstract: A circuit for the stable synchronization of an asynchronous data signal. The circuit comprises a first latch for receiving a first asynchronous data signal, a first delayed system clock signal, and a synchronized reset signal and for providing a system clock synchronized version of the first asynchronous data signal. A first delaying circuit receives a system clock signal and the first asynchronous data signal and provides the first delayed system clock signal. The circuit also includes a second latch for receiving a second asynchronous data signal which is a function of the inverse of the first asynchronous data signal and a second delayed system clock signal, and for providing the synchronized reset signal. A second delaying circuit receives the system clock signal and the first asynchronous data signal and provide the second delayed system clock signal.

Abstract: An improved PSK transmitter such as may be used in a CATV system in the up-link from terminal units to a center having a simple arrangement for switching ON and OFF the PSK carrier signal. An oscillator produces a oscillation output signal at a frequency twice that of the desired carrier frequency. The output of the oscillator is then frequency divided by an element such as a T-type flip-flop, the operation of which is switched ON and OFF by a control signal.

Abstract: A series of nodes in a telecommunications network are connected by a bi-directional transmission path. An outgoing signal passes each of the intermediate nodes in the path and sets a counter timing at each intermediate node. The outgoing signal then returns from the loop node with time information attached to it. As the returning trigger signal passes the intermediate nodes, the intermediate nodes stop counting the elapsed time since the trigger signal passed the intermediate node, and latches the time information. Precision time synchronization information is then determined for each intermediate node by halfing the two way travel time from the intermediate node to the loop node, adjusting for propagation and processing delays, and adding it to the time information from the loop node.

Abstract: An improved CMOS signal magnitude detector (SMD) for accurately quantifying the peak-to-peak magnitude of a received signal is disclosed. The SMD includes a precision gain amplifier, positive and negative peak detectors and a switched capacitive amplifier. The recited components are coupled to form a combination circuit arrangement which receives a differential signal and outputs a single ended signal which is compared with a reference signal to provide a control signal when the differential signal is of a sufficient peak to peak voltage magnitude. The control signal may be used to gate the differential signal and generate an output signal representative of received data.

Abstract: A technique for designing trellis codes to minimize bit error performance for a fading channel. The invention provides a criteria which may be used in the design of such codes which is significantly different from that used for average white Gaussian noise channels. The method of multiple trellis coded modulation of the present invention comprises the steps of: (a) coding b bits of input data into s intermediate outputs; (b) grouping said s intermediate outputs into k groups of s.sub.i intermediate outputs each where the summation of all s.sub.i,s is equal to s and k is equal to at least 2; (c) mapping each of said k groups of intermediate outputs into one of a plurality of symbols in accordance with a plurality of modulation schemes, one for each group such that the first group is mapped in accordance with a first modulation scheme and the second group is mapped in accordance with a second modulation scheme; and (d) outputting each of said symbols to provide k output symbols for each b bits of input data.

Abstract: A stuff synchronization circuit includes a memory, a phase comparison D flip-flop, a stuff judgment flip-flop, and a control section including selectors and an encoder. In the memory, writing and reading are performed at different timings. The phase comparison D flip-flop detects a phase difference between a write timing for a specific bit included in data input to the memory and a read timing for the specific bit. The stuff judgment D flip-flop judges an insertion timing of stuff pulses on the basis of the detected phase difference. The control section keeps a time interval between a time at which the phase difference is detected by the phase comparison D flip-flop and a time at which the insertion timing of stuff pulses is judged by the stuff judgment D flip-flop constant.

Abstract: Provided is an apparatus for analysing digital radio transmissions which can provide an output indicating the condition of a digital transmission link. The apparatus operates by sampling received radio signals to produce for each sampling instant a signal or signals representative of the modulation state of the transmission at the sampling instant. The apparatus includes a processor which can receive and measure a given number of such signals. The processing means is arranged to process the signals according to one or more stored routines and generate one or more parameters which indicate the condition of the transmission. The apparatus includes means for representing the samples by digitally encoded numbers and the processing means arranges those samples into one of a plurality of groups according to the value of the number. The number of groups correspond to the number of modulation states. This technique allows the apparatus to carry out accurate analysis of the transmission.

Abstract: A method of reversibly compressing a sequence x(k) of information-carrying symbols, preferably digital signals which can assume Q discrete values, K being an index assuming integral number values, and consists in that the sequence x(k) is processed in means (1) to form a residue w(k), whereafter a modulo Q operation is carried out on the residue w(k). The modulo Q reducing sequence w(k) is finally encoded to form a compressed sequence n(k), which contains the same information as the original sequence x(k). In reconstructing the sequence x(k), the compressed sequence n(k) is decoded and subsequently processed in inversion means (5) to form a sequence y(k), on which a modulo Q operation is carried out, whereby the original sequence n(k) is obtained. An apparatus for carrying out the method includes means (1), means (2) for carrying out the modulo Q operations and an encoder (3).

Abstract: A method for calibrating a remote pilot unit is provided wherein both the pilot receiver and the pilot transmitter are calibrated. A test signal of a known magnitude is applied to the pilot unit and the magnitude actually received by the pilot receiver is determined. The two magnitudes are compared and a correction signal is determined. To calibrate the remote transmitter, a signal of a nominal magnitude from the transmitter is applied to a measurement device and the determination is made by the measurement device of the actual magnitude applied. The actual magnitude and the nominal magnitude are compared and a transmitter correction signal is determined. The receiver correction signal and the transmitter correction signal are stored in permanent memory within the pilot unit. This process is repeated at a plurality of frequencies to provide a signature for both the transmitter and the receiver.

Abstract: An FSK shift keying device includes a detector for detecting a transmission frame consisting of a preamble, data, and a postamble, a time constant circuit charged in response to a voltage signal detected by the detector for generating a time constant, a charging voltage being determined in accordance with the time constant set in correspondence with a duration of high level in the preamble of the transmission frame, a reference voltage generator for generating a reference voltage signal having an amplitude value which is 1/2 an amplitude value of the voltage signal from the detector, and further generating a comparison reference voltage signal obtained by subtracting the reference voltage from the charging voltage, and a comparator for comparing the comparison reference voltage signal with the voltage signal input from the detector.

Abstract: In a modulation circuit, a variable frequency carrier is modulated by a binary PSK (phase shift keying) modulator with the digital signal of a selected data channel. A plurality of error correction values are stored in storage locations of a memory corresponding to the channels, each of the error correction values being representative of a deviation of the inherent operating characteristic of the modulator when operating at a particular frequency of the carrier from a predetermined operating characteristic. The carrier is generated by a channel synthesizer and its frequency is varied corresponding to the selected channel. The memory is addressed to read an error correction value from one of the storage locations corresponding to the selected channel. An error correction circuit is provided to correct the deviation in response to the error correction value read out of the memory.

Abstract: A data decoding circuit which receives an input signal comprising a sequence of pulses and generates a digital data output signal and timing signals in response thereto. The circuit includes a phase-locked loop which generates timing signals in response to the input signal and an offset signal from a data separator circuit. The data separator circuit generates the digital data output signal and the offset signal, which measures the degree of correlation between the input signal as received by the data separator and the timing signal from the phase-locked loop, thereby obviating the need to match the data separator circuit closely to the phase-locked loop.

Abstract: A method and device are provided for multistate modulation and demodulation with adjustable protection level, consisting in separating the binary signals, before demodulation, into critical and non critical signals, in attributing to the non critical signals all the states of the modulation and in attributing to the critical signals a reduced number of states which are, in the modulation diagram, the furthest removed from each other.

Abstract: There is disclosed a data circuit-terminating equipment (DCE) which connects a start-stop synchronous data terminal equipment (DTE) which is not synchronized with a PCM transmission line having various speeds. Further the DCE can satisfy recommendations of the V25 bis of CCITT. The DCE includes a start-stop synchronizing circuit to deliver a sampled request-to-send signal RS, a sampled send data and to transmit a clear-to-send signal CS to the DTE, a PLL obtaining a clock from the line, a timing generator generating timings for circuits, a mapping circuit mapping to make the sampled send data match into the line speed, a sending register converting transmission speed of the mapping circuit output to send to the line at the instructed period, a receiving register receiving data from the line to deliver data with the required speed during the required period for the DTE, and a demapping circuit receiving the receiving register output to demap and send to the DTE.

Abstract: A circuit arrangement for serial data transmission between a plurality of subscriber stations via a data bus with transmitters that are high-impedance in the passive condition and low-impedance in the active condition is provided with a mutual control of the subscriber stations which occurs via the data bus without the assistance of additional control lines. This is achieved in that the leads of the data bus are each connected to a voltage source at at least one location via a resistor and in that at least one evaluation device for evaluating the voltages carried by the two leads is provided, the evaluation device outputting a busy signal given voltages of different magnitude at the leads of the data bus and outputting a free signal given identical voltages at the leads of the data bus. The circuit arrangement is particularly suitable for utilization in remote control devices.

Abstract: The present invention describes a phase shift key receiver or demodulator having an A.C. couple base band automatic gain control. A pair of detectors for the automatic gain control are A.C. coupled to the output of a pair of linear analog multipliers for the purpose of eliminating DC offset signals and for minimizing thermal noise at the input of the automatic gain control circuit. The outputs of the pair of detectors connected in the data detecting branch and the carrier tracking branch of the PLL are connected to a input of the summing circuit whose output is connected to the automatic gain control loop filter. The output of the filter supplies the scaling signal employed as the scaling input to the linear analog multipliers.

Abstract: Apparatus and method for amplitude equalization of a signal channel such as a telephone line that does not require adjustments at the customer's premises. The equalization circuit receives a plurality of alignment signals at predetermined frequencies from the signal channel, and measures the amplitude of each alignment signal. The amplitudes are used to determine analog and digital filter transfer function coefficients. Thereafter, input signals on the signal channel are filtered such that the combined amplitude response of the signal channel and filter is substantially flat over a designated frequency range.