Abstract: A method and arrangement for generating a correction signal for a digital clock recovery circuit. This method cost effectively provides phase sensors that can be realized in integrated technology. In a sample-and-hold circuit, an auxiliary data clock (DHT1) that is valid as a recovered clock of a digital signal (DS1) and whose clock frequency is somewhat higher or lower than the bit rate of this digital signal (DS1) is sampled by the latter. Then a trailing edge of a pulse of this auxiliary data clock (DHT1) is identified by a status change. The sample-and-hold circuit then outputs a correction request signal (K1) that releases a correction signal (K) in a following circuit, this correction signal (K) being synchronous with the auxiliary data clock (DHT1). This method is utilized in digital clock recovery equipment.

Abstract: In some digital communications systems, such as the Integrated Services Digital Network (ISDN), problems may occur in recovering timing from signals generated by several terminals located varying distances from a common transmitter. Timing recovery is facilitated by detecting a marker of a frame transmitted to the several terminal equipments, detecting a corresponding marker receives shortly afterwards from one of the terminal equipments; and sampling the received digital signal at a sampling instant delayed relative to a specific feature of the received marker, for example, a zero crossing immediately following a frame bit. Preferably, the delay between the sampling instant and the occurrence of the specific feature used as a reference point is proportional to the time elapsed between detection of the outgoing or transmitted marker and detection of the incoming or received marker and hence proportional to the round trip propagation time.

Abstract: A frame synchronizer comprises a frame sync detector for detecting a frame sync pattern multiplexed with a data signal. First and second counters are incremented in response to an input clock signal to generate output signals at frame intervals. A mismatch detector detects a first mismatch between the output of sync detector and the output of first counter and a second mismatch between the sync detector output and the output of second counter. To reduce resynchronization period, the second counter is disabled in response to the detection of the second mismatch and its binary count is loaded into the first counter upon detection of the first mismatch. According to a different aspect, a bit synchronizer includes a plurality of latches connected to a data input terminal for respectively latching a data signal in response to a latch timing signal applied thereto. A mismatch detector is provided for detecting a mismatch between outputs of the latches.

Abstract: In a phase detection circuit for detecting the phase relation between a first (f.sub.1) and a second (f.sub.2) clock signal in which tappings (b, c, d, e, f, g, h, i) of a delay circuit (7) for the first clock signal are connected to memory elements (27, 29, 31, 33, 35, 37, 39, 41) clocked by the second clock signal and having their outputs (B, C, D, E, F, G, H, I) connected to a logic circuit (59) and in which a plurality of outputs of the delay circuit (7) is connected to a measuring circuit (89, 95) for measuring the delay time of the delay circuit, a control circuit (87, 85, 93, 91, 83, 77, 79, 81) controlled by the measuring circuit is arranged for controlling the delay time of the delay circuit at a value corresponding to the period of the first clock signal, while the logic circuit includes an AND-gate (61, 65, 69, 73) alternating with a NOR-gate (63, 67, 71, 75) for obtaining a very accurate and unambiguous phase detection, using few circuit elements.

Abstract: Method and apparatus suited for use with a decoder receiving data serially from a network is disclosed providing synchronization throughout reception and decoding of packets of symbols. An appropriately-delayed read pointer initialization strobe used by an elastic buffer portion of the receiver provides the sequence of synchronization signals which avoids deletion of bits of packet preamble.

Abstract: A timing synchronizing circuit with a phase locked loop. A multiplexor is employed to cause the phase locked loop to alternate between a self-excited mode for maintaining the frequency of a recovered timing signal and a mode in which state transitions of a baseband data signal are compared with the phase locked loop feedback signal to adjust the frequency of the recovered timing signal.

Abstract: A circuit for detecting a code violation in an alternate mark inversion signal comprises a first detecting circuit receiving the alternate mark inversion signal for generating a first detection signal at continuous occurrence of two first polarity signals without an intervening signal of a second polarity, the first and second polarity signals being indicative of the same binary logical level, and a second detecting circuit receiving the alternate mark inversion signal for generating a second detection signal at continuous occurrence of two second polarity signals without interleaving the first polarity signal. The first detection signal is inputted to a first enable signal generating circuit for generating a first enable signal having a predetermined active period, and the second detection signal is inputted to a second enable signal generating circuit for generating a second enable signal having a predetermined active period.

Abstract: A receiver of a system for transmitting data symbols at a given baud-rate comprises a symbol detector (7) operating at the baud-rate 1/T and means (6) for optimally conditioning received data symbols for this symbol detection. From the received conditioned data signal [s(k)], a phase error signal [E(K-1).c(K)] is derived that is representative of a phase difference between a locally generated baud-rate clock signal and a baud-rate clock signal inherent to the received data symbols, and the receiver comprises means (11, 12) for the reduction of this phase difference step-by-step in response to the phase error signal [e(k-1).c(k)]. This receiver further includes an accumulator (44) for determining the mean value [u(k)] of the phase error signal over a predetermined number (M) of symbol intervals and a detector (45) for establishing whether this means value [u(k)] is situated in a zone whose boundaries [.+-..sub.V r(k)/N] are determined by a given fraction (1/N, N>1) of the level [V.sub.

Abstract: An improved complex bandpass digital filter is disclosed. According to the invention, a complex bandpass digital filter having symmetric complex coefficients is implemented using a ROM look-up table. In operation, an input bit stream is latched at a desired decimation rate and the resulting latched bits are then used to address a ROM according to the following two-cycle process: First, the bits are applied in nomal order to the ROM to obtain the real (in phase) portion of the filter output. Second, the bits are bit-reversed and then applied to the same ROM to obtain the imaginary (quadrature) portion of the filter output. Thus, complex outputs are obtained as a time-multiplexed stream from one ROM, resulting in reduced ROM storage capacity requirements.

Abstract: Apparatus for combatting intersymbol interference and noise introduced into a data signal transmitted at a symbol rate l/T by a transmission channel having a memory span LT corresponding to a number of L consecutive data symbols, comprises a receive filter (RF), a first decision circuit (ID) for forming preliminary symbol decisions in response to the transmitted data signal, a second decision circuit (FD) for forming final symbol decisions, means (FFS and FBS) for compensating pre- and post-cursive intersymbol interference, and a combining circuit (AD) for forming the input signal for the second decision circuit (FD).

Abstract: A data transfer synchronization method and circuit allows data to be transferred between two synchronous systems running asynchronously with each other in a way that does not require the receiving system clock to be running twice as fast as the source system clock. Data is clocked into a first set of flip-flops by the clock signal of the source system. The source system clock signal is also used to toggle a toggle flip-flop. The receiving system clock signal is used to clock a first clock bit flip-flop coupled to detect the state of the toggle flip-flop. A delayed version of the receiving system clock signal is used to clock the output of the first set of flip-flops into a second set of flip-flops. The normal (undelayed) receiving system clock signal is used to clock the output of the second set of flip-flops into a third set of flip-flops.

Abstract: A communication interface for connection to a communication apparatus provided with a balanced-type interface circuit includes a circuit for outputting a constant voltage approximately at the middle of the voltage level of transmitted data signals and is adapted to transmit to a balanced-type receiver contained in the communication apparatus a data signal as one input and the constant voltage from the constant-voltage circuit as another input.

Abstract: A parallel asynchronous elasticity buffer. Selection of the address of a storage element for writing or reading of data is provided by asynchronous input and output pointers implemented using circular gray code counters. The buffer is initialized once during transmission of each frame of data so that the pointers do not select the same storage element for writing and reading at the same time. Write overflow or read underrun of a storage element is detected before any data corruption can occur by comparing the input and output pointers. An error condition is detected if the input and output pointers overlap for a threshold period, which can be shorter than the period required for writing or reading of a multibit data unit to or from the buffer. The overlap time period is determined by comparing the pointers at one or more sampling times corresponding to selected phases of a clock signal.

Abstract: A frame synchronization device for a synchronous digital bit stream divided into blocks by means of a block code and structured in frames comprises a frame alignment word configuration recognition circuit generating for each recognized configuration a recognition signal that is directed to a frame alignment acquisition control circuit through the intermediary of a configuration selection circuit. This circuit operates under the control of a time window definition circuit driven by a block timebase and a frame timebase and is adapted to select only recognition signals corresponding to alignment word configurations correctly placed relative to the blocks. The sorting done by the configuration selector eliminates most imitation alignment words and therefore accelerates significantly the synchronization process.

Abstract: A receiver circuit recovers the phase of the carrier of a received MSK signal so that conventional synchronous detection techniques can be employed to demodulate the received signal. A quadrature receiver circuit (204-214) processes the received MSK signal to produce in-phase and quadrature phase baseband signals. These I-channel and Q-channel baseband signals are viewed as one signal which is expressed as a complex number; the I-channel forming the real part and the Q-channel forming the imaginary part. The baseband signal is multiplied (218 and 220) by odd and even orthogonal functions (222 and 224) and then integrated (226 and 227) over odd and even numbered two bit periods, respectively. The odd orthogonal function begins and ends on odd numbered two bit periods of the received MSK signal, while the even orthogonal function begins and ends on even numbered two bit periods. The result of the integration is a single complex number for each bit of the received signal.

Abstract: An electronic data storage, transmission and retrieval apparatus and method wherein a combination power and data signal is received by a preferably portable and miniature data storage means which in turn modulates the combination signal in acordance with available data signals. Substantially simultaneous and bi-directional data communication can be achieved between a data link means and a data storage means without physical contact between the devices.

Abstract: A jitter attenuation circuit includes a FIFO data register (10) which is operable to receive data that is synchronized with a Write clock output therefrom synchronized with a Read clock. The data is written to the FIFO register (10) from a location determined by a Write pointer (12). The data is read out from the FIFO register (10) from a location determined by a Read pointer (14) which is clocked by a Read clock. The Read clock is synchronized with the Write clock by a phase lock loop (24). The phase lock loop (24) has a phase detector (26) which is operable to accrue phase error over intervals of 2.pi. radians such that the phase lock loop (24) virtually never loses lock as a result of phase jitter on the Write clock.

Abstract: In a trellis coding arrangement, the alphabet is comprised of a plurality of cosets of a sublattice of a p-dimensional lattice, where p<4.

Abstract: A method and apparatus detects synchronizing sequences in a digital data stream. The apparatus comprises a plurality of candidate sequence generators and associated vote counters which are used in conjunction with comparators to test the order of received synchronizing symbols of a predefined sequence of predefined symbols against a plurality of corresponding candidate symbols of candidate sequences. A candidate generators begins a new candidate sequence when an ambiguity in the input symbol sequence is detected, i.e., when a received symbol does not match a candidate symbol of one of the previous candidate sequences. The apparatus includes a voter decision logic circuit which selects a winner among the candidates based upon the number of votes or matches tallied for each candidate sequence.

Abstract: A single data recovery integrated circuit is used to achieve a data recovery system which can operate at multiple selected frequencies. A time delay adjustment circuit is connected to the data recovery IC and sets the time delay. A frequency controller circuit is connected to the data recovery IC and sets the data recovery IC at the desired frequency. A frequency adjustment circuit is connected to the data recovery IC and adjusts an oscillator of the data recovery IC. A stabilizer circuit is connected to the frequency controller circuit and the data recovery IC and ensures the integrity of the phase locked loop.