Patents Examined by Mark E. Nusbaum
  • Patent number: 4493020
    Abstract: A microprogrammed data processing system is provided in which each high level instruction is performed by one or more tasks, each task being in turn performed by executing one or more task microinstructions in a microprogrammed manner. Dynamic resource allocation is provided by employing a plurality of dynamically allocatable registers whose free and use states are continuously monitored in an allocation register. The outputs of the allocation register are used as an address for a register allocation memory which is mapped so as to identify a particular group of free registers which are available for assignment for each new task in response to the allocation register address.
    Type: Grant
    Filed: July 29, 1980
    Date of Patent: January 8, 1985
    Assignee: Burroughs Corporation
    Inventors: Dongsung R. Kim, John H. McClintock, Jr.
  • Patent number: 4455606
    Abstract: This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.
    Type: Grant
    Filed: September 16, 1981
    Date of Patent: June 19, 1984
    Assignee: Honeywell Information Systems Inc.
    Inventors: David E. Cushing, Richard A. Lemay, Philip E. Stanley, William E. Woods
  • Patent number: 4454576
    Abstract: A system for use in an electronic digital signal processor for assembling multiple report definition instructions to create a shell document to generate a file report. The system enables an operator to depress an instruction key to call up an instruction menu and select for display the report definition instruction menu. The operator chooses report instructions desired in any order, and the system inserts chosen instructions in proper order to build the shell document. The operator keys report information in between the instructions. The shell document is stored in machine-dependent language to enable the document to be redisplayed in operator-dependent language as determined by the current program loaded in the processor.
    Type: Grant
    Filed: May 18, 1981
    Date of Patent: June 12, 1984
    Assignee: International Business Machines Corporation
    Inventors: John W. McInroy, Paul D. Waldo, Jo A. Elliott, Thomas L. Adam, Freddie R. White
  • Patent number: 4447871
    Abstract: A data communication system which includes a data distributor, a communication station and a plurality of front-end-processors. These front-end-processors are connected with a computer through a common bus. The distributor distributes the data received by the station to one available front-end-processor, which preprocesses the received data, and transfers the pre-processed data to the computer through the bus. By operating the front-end-processors in parallel with respect to successively received packets of data, the processing speed of the system is increased.
    Type: Grant
    Filed: February 2, 1981
    Date of Patent: May 8, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Matsuaki Terada, Koji Yokota
  • Patent number: 4443846
    Abstract: There is described a unique apparatus for exchanging commands and data via a dedicated memory which has ports connected to the data and address busses of two different microprocessors. The system operates even though the microprocessors have different word lengths, e.g. a sixteen bit processor and an eight bit processor. The system permits interfacing between the microprocessors with different bit size words and allows each of the microprocessors to treat the exchange memory as part of its own memory space without locking one microprocessor off of a shared bus.
    Type: Grant
    Filed: December 29, 1980
    Date of Patent: April 17, 1984
    Assignee: Sperry Corporation
    Inventor: Ralph L. Adcock
  • Patent number: 4441161
    Abstract: A programmable sequence control apparatus including a first memory device for storing sequence program instructions, an input/output device, a relay ladder operation device for executing logic operations for a relay ladder circuit having n rows and m columns (wherein n and m are positive integers) in accordance with the program instructions, and a control device for delivering control signals to the relay ladder operation device, is so constructed that the control device includes a memory device for storing contact data and branch data for one column j (wherein j=1, 2, . . .
    Type: Grant
    Filed: April 9, 1981
    Date of Patent: April 3, 1984
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Junichi Sasaki, Yoshihiko Okayama
  • Patent number: 4434465
    Abstract: A microcomputer device is disclosed containing a read-only memory for programs, a read/write memory usually containing data, and a CPU, all in a single integrated circuit. The CPU is microprogrammed in that each instruction word fetched from the program memory initiates a sequence of microinstructions to perform the operation defined by the instruction word. The sequence is determined by addresses for a control ROM, and the addresses are selected by a method referred to as dispatching. The control ROM output includes a jump address by which the next address may be any location in the entire control ROM address range. Alternatively, the jump address may be modified by any one of several dispatches. A group dispatch selects one of the modes of accessing source and/or destination operands, based on one field of the instruction word. A subsequent function dispatch selects one of the set of available arithmetic/logic operations to be performed in the CPU based on another field of the instruction word.
    Type: Grant
    Filed: April 13, 1981
    Date of Patent: February 28, 1984
    Assignee: Texas Instruments Incorporated
    Inventors: Kevin C. McDonough, John W. Hayn, Jeffrey D. Bellay
  • Patent number: 4434460
    Abstract: Hierarchical three-level computer system for receiving input messages from signal sources (23) and for conditionally activating output devices (26) according to input messages; the system comprising a host computer (15), a terminal computer (27) and a number of micro computers (22). The central computer enters condition tables into specific storage modules (2A-2E) within the terminal computer. These tables can be displayed on the terminal computer screen (10) and may be updated from the terminal computer keyboard (8). The micro computer receives input signals from a signal source (22) and composes input messages, which are transferred to the terminal computer. The terminal computer makes a comparison between input messages and condition table data and selectively activates the output devices (26).A specific up and down counting apparatus within the micro computer enables a simultaneous signal detection and data processing operation.
    Type: Grant
    Filed: June 18, 1980
    Date of Patent: February 28, 1984
    Assignee: International Business Machines Corporation
    Inventors: Karl-Gunnar Drakenborn, Mats A. Enser, Kurt G. E. Grebner, Erik I. Wallmark
  • Patent number: 4432063
    Abstract: Apparatus for moving a robot arm through a series of nonprogrammed points defining a nonprogrammed path in response to coordinate data supplied by an external device. During the automatic execution of a programmed cycle of operation, a robot control causes the robot arm to move to a predetermined programmed position; and in response to a programmed external path control code, an external path control generator serially provides position data defining the nonprogrammed points. The robot control moves the robot arm through the nonprogrammed points, after which the programmed cycle of operation is continued.
    Type: Grant
    Filed: October 6, 1981
    Date of Patent: February 14, 1984
    Assignee: Cincinnati Milacron Inc.
    Inventor: Brian J. Resnick
  • Patent number: 4430699
    Abstract: A distributed data processing system having several local systems (LS) between which communication is provided via clearly defined functional layers. A functional coordination layer managed by systems intercommunication processors (SIP) is responsible for the functions of coordination, communication, control, initialization and simulation relative to the LSs. A functional communication layer managed by communication modules (CM) is responsible for the communication protocols between the LSs. A functional transport layer including transmission modules (TM), a looped optical bus and a looping unit (LIG) element. A description of each LS is contained in its SIP in the form of descriptive tables facilitating the use of the resources of the global system by any LS via parameter translations, local to global to local, each communication between LSs being performed in the form of a transaction having separate interrogation, auto-selection, presentation, processing and result return phases.
    Type: Grant
    Filed: February 17, 1981
    Date of Patent: February 7, 1984
    Assignee: U.S. Philips Corporation
    Inventors: Gerard Segarra, Francois J. Phulpin
  • Patent number: 4430710
    Abstract: A dual-processor, general purpose mini-computer which is programmed as a front-end data communications processor and is called a Network Support Processor. Data transfer commands received from a main host computer are executed and result messages are returned to the main host computer by the Network Support Processor. A base connection module providing slide-in connector cards houses and supports circuit cards which make up the Network Support Processor. These cards include a master controller which includes a master processor card, a master memory control card and an Interface Card which connects to a main host computer and to one or more line communications processors, each of which may handle up to 16 data communications lines. A slave controller likewise includes a slave processor circuit card, and a slave memory control circuit card. A series of slide-in memory cards forming a shared memory storage means connect to both the master and the slave memory control circuit cards.
    Type: Grant
    Filed: August 24, 1981
    Date of Patent: February 7, 1984
    Assignee: Burroughs Corporation
    Inventors: Robert D. Catiller, Craig W. Harris, Ronald D. Mathews
  • Patent number: 4428045
    Abstract: Improved apparatus for specifying and resolving addresses of operands in a digital data processing system. Instructions executed by the system are contained in procedures. Addresses are calculated using a set of architectural base addresses. Operands are represented in the instructions by means of names. The names include immediate names, which directly specify one of the architectural base registers and a displacement, and table names, which specify a name table entry in a name table associated with the procedure. The name table entry specifies how the address of the operand represented by the table name may be derived using the architectural base addresses and information contained in the name table. Each name table entry includes a basic name table entry. The basic name table entry contains a base source specifier and a base or displacement specifier.
    Type: Grant
    Filed: September 11, 1981
    Date of Patent: January 24, 1984
    Assignee: Data General Corporation
    Inventor: Gary Davidian
  • Patent number: 4425624
    Abstract: In order to simulate an instantaneous temperature-rise of a thyristor through which flows a current (I), this device takes the mean value (VM) of that current and squares the effective value (EC) thereof. An image of the dissipated power obtained at the output of an adder (S) is applied to devices (K.tau.ra,, K.tau.jb) for simulating radiator-environment, housing-radiator and junction-housing thermal time-constants, respectively. An adder (S.sub.1) provides the image i (.DELTA..theta.) of the temperature-rise.
    Type: Grant
    Filed: June 10, 1981
    Date of Patent: January 10, 1984
    Assignee: La Telemecanique Electrique
    Inventor: Jean P. Planche
  • Patent number: 4424561
    Abstract: A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.
    Type: Grant
    Filed: December 31, 1980
    Date of Patent: January 3, 1984
    Assignee: Honeywell Information Systems Inc.
    Inventors: Philip E. Stanley, Richard P. Brown, Arthur Peters
  • Patent number: 4424571
    Abstract: An apparatus for electrically simulating a reciprocating gas pump or compressor includes unidirectional devices for simulating intake and discharge valves. The volume of the reciprocating cylinder is modeled by a fixed capacitor coupled in a feedback arrangement with a variable gain amplifier. The gain of the amplifier is preferably controlled by the contents of a digital memory device, which varies the gain to simulate the pumping action of a compressor. The device provides voltage outputs representing the pressure and volume readings obtained in the compressor being simulated.
    Type: Grant
    Filed: June 29, 1981
    Date of Patent: January 3, 1984
    Assignee: Southern Gas Association
    Inventor: Carl E. Edlund
  • Patent number: 4422142
    Abstract: A system for controlling a plurality of microprocessors, comprising a common memory which can be selectively switched to exclusive buses which are connected to the plurality of microprocessors, respectively, and a priority control circuit which determines the priority of the microprocessors. According to the system of the present invention, it has a common memory that is selectively connected to the buses, data is transmitted without affecting the operation of the microprocessors on the receiving side, data transfer between the microprocessors having different cycle times is carried out at speeds that are adapted to the cycle times of the individual microprocessors, and the degree of the exclusive use of the bus by the microprocessor is prevented from being reduced when the direct memory access transfer is carried out. Consequently, a system for controlling a plurality of microprocessors having an improved performance is obtained in accordance with the present invention.
    Type: Grant
    Filed: June 17, 1980
    Date of Patent: December 20, 1983
    Assignee: Fujitsu Fanuc Limited
    Inventors: Hajimu Inaba, Hideo Miyashita, Shoichi Otsuka
  • Patent number: 4419732
    Abstract: An improved inner loop control is disclosed for use in an aircraft pitch axis control system. Signals representative of vertical acceleration and pitch rate are complementary filtered and summed to produce an "inner loop" damping signal which is combined with "outer loop" command signals to produce an elevator control signal. The improved approach provides higher outer loop control law gains and better system stability, resulting in higher control bandwidth and tighter command tracking, especially in turbulence.
    Type: Grant
    Filed: September 14, 1981
    Date of Patent: December 6, 1983
    Assignee: The Boeing Company
    Inventors: Antonius A. Lambregts, Rolf Hansen
  • Patent number: 4419728
    Abstract: The subject channel interface circuit functions to provide a high speed interface between a processor and a data link, which link carries data messages having virtual addresses. The message handler is programmable and serves to translate the header portion of the data message from a virtual address into a hardware memory address, which is used to activate a specific location in the processor memory. The data portion of the data message is then directly inputted to this memory location (i.e., DMA) and the appropriate file pointers are reset. When a complete file is received and stored in memory, the message handler generates a processor interrupt.Thus, the subject message handler performs all the data receiving tasks, including file storage and linking, without requiring the involvement of the associated processor.
    Type: Grant
    Filed: June 22, 1981
    Date of Patent: December 6, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Allen L. Larson
  • Patent number: 4418383
    Abstract: A Large Scale Integration (LSI) data flow component is described for use as a building block, the component being capable of use singly or in combination to provide data flow paths and functions of different data widths for a processor or microprocessor. A component with an eight-bit data flow is described as a "byte slice", wherein individual byte control is provided within a multiple-byte configuration so that single data flow components within the group can operate independently of other components under control of external logic. Components may operate on a stand-alone, a multiple-byte, or nonactive-byte basis. A control scheme permits functions of one component to be influenced by actions or logic of another component to permit efficient implementation of arithmetic algorithms.
    Type: Grant
    Filed: June 30, 1980
    Date of Patent: November 29, 1983
    Assignee: International Business Machines Corporation
    Inventors: Donald E. Doyle, George A. Hellwarth, Jack L. Quanstrom
  • Patent number: 4418384
    Abstract: A data processing system operating in a bit oriented protocol (BOP) mode of operation senses a transmit underrun; that is, the subsystem is not receiving data from a microprocessor fast enough to maintain the synchronous transmission over the communication line. Apparatus senses the transmit underrun state and generates an abort sequence of bits containing from 8 to 13 successive binary ONE bits.
    Type: Grant
    Filed: October 6, 1980
    Date of Patent: November 29, 1983
    Assignee: Honeywell Information Systems Inc.
    Inventors: Thomas O. Holtey, Richard P. Kelly, Steven S. Noyes, James C. Raymond