Abstract: A microprocessor numerical control system having a prom module which contains the operating program of the system and a processor module which contains a microprocessor generating multiplexed data and address information on an internal bus. The processor module further includes bus control logic and address and data transceivers which interface the internal bus with the system's address data and control buses. The processor module further includes a variety of timing and interrupt control circuits which permits selective communication with other modules in the system. The system further includes a peripheral interface module having thereon logic to communicate with a CRT, keyboard, audible and visual indicators and an A to D converter which may be used to input feedrate override information into the processor memory.

Abstract: A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the address. When a disagreement is detected through the comparison, it is counted; however, the count operation is inhibited if the data read out from the fault-address memory is a fault data. When the counted number exceeds a predetermined value, a fault signal is generated. After the test is terminated, an address counter is operated, the fault-address memory is read out by the content of the address counter, and when fault data is detected from the output read out, the content of the address counter is fetched into the CPU.

Abstract: The present invention relates to pipeline processors having testing means for identifying malfunctioning modules and for testing the self-testing means themselves. The testing employs the parity check principle and provides an on-line test of memory modules and an off-line test at the processor clock rate of both memory and arithmetic modules. The means for testing include a parity encoder associated with each module and a comparator which couples parity "comparison values" to a priority encoder, operating at the high speed clock rate of the pipeline processor. The test results are then supplied to a RAM, also operating at the clock rate of the pipeline processor. With the test results in the memory, a microcomputer is provided to search the memory at a slower rate for the highest priority failed module.

Abstract: Various size frames or pages of information elements stored in a computer system can be simultaneously displayed on a screen-based terminal. The computer processor identifies the screen position the user selects for each of the stored pages and the top-to-bottom order of the pages with respect to visibility in the event that pages overlap. The processor selects the pages in descending order, topmost page first. Information elements of selected pages are transferred to appropriate locations in a display memory only in the event that an auxiliary memory registers that an information element has not priorly been transferred to those locations. After all the pages are transferred, background data is written into each display memory location that the auxiliary memory registers as not having an information element transferred thereto. The display memory is scanned in a conventional manner to apply the display information therein to the viewing screen.

Abstract: A dual deadman timer circuit functions to reset a dual mode microprocessor in the event of loss of program control. The microprocessor has high and low power requirements corresponding to its two operating modes, and the deadman timer circuit also adjusts the output power level of an associated two-level power supply to ensure that sufficient power is available for the full operation of the microprocessor during reset. The deadman timer functions during both microprocessor modes and includes two level-sensitive input sections to ensure that the microprocessor is reset under an error condition.

Abstract: An electronic translator is provided in which any of a plurality of groups of words, such as sentences, idioms and phrases can be translated from a first language into a second language in response to the input of a single word from one or more of the groups of words in the first language. An additional word can be entered in some embodiments so as to function in the same manner as the single word. At least two types of memories are provided for storing data representing each of the groups of words and their translated equivalents respectively. A detection circuit is provided for detecting whether the single word is equivalent to a word in any of the groups of words retrieved from one of the memories. An address circuit is provided for addressing each of the two memories so as to cause retrieval of the groups of words and their equivalent translated words.

Abstract: A modular read-write and read-only memory unit capable of employing both direct and indirect decimal and symbolic addressing, a central processing unit capable of performing both serial binary and parallel binary-coded-decimal direct and indirect memory register arithmetic, and an input-output control unit capable of bidirectionally transferring information between the central processing unit and a number of input and output units are controlled by a microprocessor included in the central processing unit. The input and output units include a keyboard input unit with a section capable of being defined by plug-in read-only memory modules and stored programs added by the user, a magnetic card reading and recording unit capable of bidirectionally transferring information between an external magnetic card and the calculator, and a solid state output display unit capable of displaying three lines of numeric information.

Abstract: Method of operating a mains-powered processor-controlled electrical apparatus when the power fails and is subsequently restored and apparatus therefor. In the case of a power outage data identifying the program in progress is transferred for salvage to a memory. When power is restored and if the duration of the mains-power failure is smaller than a predetermined value, physical parameters which define the instantaneous state of the apparatus are sensed in response to an instruction from the processor in order to determine the conditions under which the program may be resumed by the apparatus.

Abstract: The disclosure pertains to a relatively small local storage (LS) in a processor's IE which can be effectively expanded by utilizing a portion of a processor's store-in-cache. The cache allocates a line (i.e. block) for LS use by the instruction unit sending a special signal with an address for a line in a special in main storage which is non-program addressable (i.e. not addressable by any of the architected instructions of the processor). The special signal suppresses the normal line fetch operation of the cache from main storage caused when the cache does not have a requested line. After the initial allocation of the line space in the cache to LS use, the normal cache operation is again enabled, and the LS line can be castout to the special area in main storage and be retrieved therefrom to the cache for LS use.

Abstract: A data processing system having a plurality of processors and a plurality of dedicated and shared memory modules. Each processor includes a cache for speeding up data transfers between the processor and its dedicated memory and also between the processor and one or more shared memories. The integrity of the data in each cache with respect to the shared memory modules is maintained by providing each shared memory with a cache monitoring and control capability which monitors processor reading and writing requests and, in response to this monitoring, maintains an accurate, updatable record of the data addresses in each cache while also providing for invalidating data in a cache when it is no longer valid.

Abstract: A method for transferring control between hierarchically related cooperating sequential processes P and Q executable in a multi-processing CPU environment. The method uses pointers to identify active and suspended processes. The method steps comprise generating and memory storing activation records; transferring control from process P to process Q, and updating the process pointers to record the suspension of process P and the activation of process Q; and resuming execution in the most recently executing subprocesses of Q by reference to the process pointers.There is stored in memory one activation record per process. The record includes a pointer to the activation that is the parent of the process, a pointer to the most recently executing subprocess of the process, and information defining the current execution state of the process. These pointers are further constrained such that the set of activation records form the nodes of a tree whose arcs are defined by the parent pointers.

Abstract: A peripheral device subsystem enables its peripheral devices to operate asynchronously with respect to attaches hosts through the use of managed buffers, new multiple data transfer modes, control and error recovery operations. In a preferred first or buffer mode of operation, all data of each record being transferred can be resident in a buffer before transfer to either a host or device. For a host to device write transfer, receipt of such a record by the buffer results in the subsystem signaling to the host a completion of a transfer to an addressed device even though the device has received none or only part of the data. In a second or tape write mode, recording data in a peripheral device, such as a tape recorder, completion of recording is not signaled until after the buffer has transferred the data to the recorder.

Abstract: Apparatus for monitoring and controlling the operation of a program-controlled computer. The program causes the computer to produce a signature waveform characteristic of proper computer operation at a dedicated output. The presence or absence of this waveform indicates whether or not the computer is operating properly. The apparatus monitors this output and the power supply conditions applied to the computer. Whenever the power supply is operating outside of certain limits the apparatus produces a reset signal to the computer and a disable signal to any equipment which is being operated under control of the computer. If a malfunction occurs in the computer operation, the apparatus produces the disable signal and a reset pulse. If the malfunction is cleared during reset, the computer returns to normal operation upon termination of the reset pulse.

Abstract: A keyboard access system is provided for interfacing a keyboard and the programs of a text processing machine. The keyboard has typamatic function keys, i.e., nontypamatic keystroke information is generated by the keyboard upon depression of a key and, after a short delay, additional typamatic keystroke information is generated as long as the key is held down at a constant rate. The keystroke information represents a key on the keyboard and may also represent the meaning of the key as determined by the state of one or more prefix keys. A keystroke queue is provided for storing keystroke information passing through the keyboard access system. If the keystroke information entered into the keyboard access system is not typamatic, the system will enqueue the information in the keystroke queue and generate an audio feedback signal when the keystroke queue is not full. If the keystroke information is typamatic, the keystroke information will be compared to a table of valid typamatic function keys.

Abstract: A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue start timing control apparatus which couples to the modules and to the queue circuits for resolving conflicts between the types of requests and the internal operations required to be performed by the controller within a minimum of time.

Abstract: A digital editing system includes first and second memories in which audio data and weighting factor data are respectively stored. The audio data are sequentially retrieved from the first memory and multiplied by corresponding weighting factor data retrieved from the second memory. A coincidence detector detects when predetermined storage locations of the memories are addressed. The weighting factor data has a unity or zero value during the time prior to the occurrence of an output from the detector, whereupon it changes its value as a function of time until it reaches to zero or unity and remains at the final value thereafter. The direction of variation of the weighting factor data can be appropriately selected to modify the audio data into a so-called "fade out" of "fade-in" pattern at a desired point of the audio program. A pair of such editing systems is required for editing audio programs from different sources for storing such programs in a pair of first memories.

Abstract: An electronic cash register includes a printer system for printing out a transaction data on a receipt bill or a journal paper. A print preset system is provided for selectively printing out the transaction data. A print inhibition preset key develops a print inhibition command which is stored at the last bit of a memory address of the corresponding transaction data. In a normal registration operation mode, a signal detection circuit functions to detect the print inhibition command stored in the last bit. When the print inhibition command is detected, the signal detection circuit functions to preclude the transaction data stored in the corresponding memory address from being transferred to the printer system.

Abstract: Apparatus for implementing a single computer instruction for moving a binary number of from one to four characters, with the characters of a given binary number having either eight or nine bits per character, from storage in a word addressable memory to a designated addressable register. The characters of the binary number are stored in the word addressable memory with each word of memory being divided into four 9-bit bytes. The most significant character of the binary number can be stored in any designated byte position of a word location with the characters of the number stored in contiguous byte locations in descending order of significance. The apparatus causes the binary number to be stored in the designated addressable register with the binary number being right justified in that register. Higher order bit positions of the register not needed to store the bits of the binary number will have stored into them fill bits or the sign bit of the number.

Abstract: The system is applied to a lathe and allows control of the machine to be adapted in such manner as to make use of the maximum power of the spindle motor with the maximum feed of the tool and the minimum cutting speed. The feed rate and the cutting speed are defined by the programmer only as the permitted region within which these parameters must jointly lie. The control unit tends constantly to command the feed rate and the spindle motor in such manner as to be within this region. Then the control unit compares the power consumed by the spindle motor, which is detected by a circuit through the armature current, with the maximum power of the motor for the actual working conditions and tends to cause the feed rate and the number of revolutions to be adapted in such manner as to make use of this maximum power. The system is adapted to exclude adaptation during cutting-in-air operation.

Abstract: A data processing system includes a number of input/output devices coupled to a communication multiplexer by 1 synchronous communication line and a number of asynchronous communication lines. During the polling operation, receive communication lines have high priority and transmit communication lines have low priority. Apparatus in the polling logic gives the synchronous communication line in the receive mode first priority and the synchronous communication line in the transmit mode second priority.