Abstract: A data processing system having a communications subsystem operating in a byte control protocol mode includes apparatus for establishing byte synchronization between the data circuit terminating equipment (DCE) and the communications subsystem. The apparatus includes a flop for receiving a stream of predetermined binary bits, a counter generating count signals indicative of the number of binary bits between a byte timing signal from the DCE and the last binary ONE bit of the last byte containing all binary ONE bits, a shift register for the serial shifting of the transmitted data bits and a multiplexer responsive to the count signals for selecting the shift register terminal, thereby timing the byte timing signal to the binary bit stream of data bits, including bytes of all binary ONE bits and a byte of all binary ZERO bits, followed by bytes of data bits.

Abstract: A method and a circuit arrangement are disclosed for transmitting binary signals between peripheral units which are connected to one another via a central bus line system. The signal transmission is to take place without the necessity of including a central processor, which is likewise connected to the central bus system. For this purpose, it is provided that signal transmission requests from the individual peripheral units are transmitted to a memory access device which is also connected to the central bus line system and which, in response to the receipt of such transmission request, de-activates the central processor in respect of the transmission of signals to the central bus line system.

Abstract: A variable limit is utilized to prevent a position controller which requires a velocity set point signal from overdriving a stuck control valve. Control based on a comparison of the actual position to desired position is utilized unless the valve is stuck. If the valve is stuck, the variable limit controls the velocity set point provided to the position controller until such time as the valve becomes unstuck.

Abstract: Incoming and outgoing lines on opposite sides of a PCM coupling network, each carrying a recurrent frame with a multiplicity of 8-bit channels which are to be individually tested, have branches extending to an input-side data extractor and an output-side data extractor of substantially identical construction co-operating with a control device such as a microprocessor serving to compare the data extracted in a given time slot from an incoming line with those extracted in a corresponding time slot from an outgoing line coupled thereto. Each extractor, realized in integrated circuitry, comprises a multiplexer for selecting one of the associated lines, a register storing the identity of the line to be selected, and presettable counters stepped by a time base synchronized with the PCM system for enabling the loading of an output register by the multiplexer at the instant when a byte of the desired channel appears on the chosen line.

Abstract: A multiprocessor system comprising a plurality of processors and a memory unit which are connected through a common bus whereby each processor communicates with the memory through the bus. Communication among processors is effected by storing in a plurality of memory zones the messages intended for the several processors. The memory zones are each dedicated to one processors, but are accessible to all the processors. The communication among processors is performed by sending a notify signal on the common bus which is identified only by the processor for which it is intended. The notify signal is acknowledged by the notified processor without interrupting its ongoing operation. The notified processor subsequently accesses the memory unit and reads the message in the appropriate memory zone.

Abstract: An apparatus is disclosed for modifying the motion of a tool centerpoint associated with the function element of a robot arm. The motion to be modified is produced during an automatic mode of operation in which the tool centerpoint travels along predetermined paths between programmed points at a programmed velocity. The apparatus is effective to modify the motion during the automatic mode in response to sensed deviations from the predetermined path. Two alternative schemes of modifying the motion are disclosed. A first alternative scheme returns the tool centerpoint to the predetermined path before it reaches the programmed point defining the end of the path. A second alternative scheme produces a new end point offset from the programmed end point and effects motion along offset paths which are translated and rotated from the predetermined paths defined by the programmed points.

Abstract: A bus interconnects a plurality of elements to form a distributed signal processing system. When two or more elements attempt to use the bus simultaneously, a method of arbitration occurs whereby each element places its element arbitration code on assigned lines of the bus forming a composite complementary code. Arbitration apparatus in each element determines an element's priority relative to other elements based on said composite complementary code. The lower priority elements drop off the bus until only the highest priority is left whereupon it uses the bus to transmit its block of data.

Abstract: An improved data processor control subsystem in which a cycle counter having a plurality of cascade-connected stages also comprises one or more supplemental or dummy stages, which can be selectively inserted or removed from the chain of cascade-connected stages, to alter the number of sub-cycles in an operating cycle, thereby decreasing the complexity of associated decoding circuitry.

Abstract: A computer arrangement for facilitating the sharing of information among computers at a memory level. Each computer includes means for accessing the main memory of another computer of the complex at machine word level, means for transmitting an interruption instruction from itself to the arithmetic control unit of the other computer, means for detecting a problem in the arithmetic control unit of itself, and means for altering one section of the logic address viewed from itself to some of a plurality of physical address spaces such as to make the same the logic address of a shared information storage region of the computer complex viewed from the program of each of the member computers. Shared information required for each computer is stored in its own main memory. When a problem occurs in the computer having the aforesaid shared information storage region it becomes evident in the computer's arithmetic control unit. As a result, an interruption instruction is sent to each of the other computers.

Abstract: The disclosure detects and handles synonyms for a store-in-cache (SIC). A processor cache directory (PD) is searched in a principle class addressed by a subset of bits taken from a processor request's logical address. The class address has both translatable and non-translatable bits. If any of the set-associative line entries in the principle class contains the request's translated address, the data is accessed in a corresponding line location in the cache. If the principle class does not have any entry with the request's translated address, a cache miss signal occurs which causes a line fetch command to be generated for main storage to fetch the required line. The line fetch command also causes synonym search circuits to generate the address of every potential synonym class by permutating the translatable bits in the principle class address provided in the line fetch command.

Abstract: A new instruction called Test Subchannel assures that one processor will not begin an I/O operation with device status information that has been outdated by an operation of another processor. When a device has status to present, a status pending bit and an interruption pending bit are set in the channel subsystem and an interruption request is made. When a processor accepts an interruption, the channel system resets the interruption pending bit but not the status pending bit. The processor that accepts the interruption updates the unit control block (UCB) in main store and resets the status pending bit in the subchannel unless the UCB has been locked by another processor that is starting an I/O operation on the same device. This invention prevents the other processor from operating with outdated status information in the UCB. A processor that has locked the UCB uses Test Subchannel to test the Status Pending bit in the subchannel. If status is pending, the processor executes a routine to update the UCB.

Abstract: In executing and controlling internal data flow for a particular program, it is often necessary to delay execution of an instruction by the insertion of an appropriate number of wait cycles. Thus, it may be necessary to interrupt instruction execution, for example, to insert a given number of wait cycles for channel access to common storage of the data processing system, for reloading a data or instruction buffer, or for a like situation. In such cases, the control unit has to ignore the particular instruction awaiting execution and execute another forced operation instead.An appropriate code is provided for a NO OPERATION instruction, say all bits zero. When a forced operation is to be executed, this code can be generated with fewer logic means at the output of the instruction register. As a result, there are no control signals active at the output of the decoder. The signals indicating forced operations have to be considered by the decoder only if a control signal is to be generated.

Abstract: An allocation controller providing for equal priority sharing of multiple resources by a plurality of central processing units. Conflicts resulting from simultaneous requests from several CPUs for access to one of the common resources are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.

Abstract: An allocation controller providing for equal priority sharing of duplicate copy multiple resources by a duplex plurality of central processing units. Conflicts resulting from simultaneous requests from several CPUs for access to one of the common resources are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.

Abstract: A cache/disk subsystem includes a storage control unit, a relatively low capacity high speed cache store, and a higher capacity slower memory such as a plurality of disk drive devices. The storage control unit controls the subsystem to transfer from the cache store to the disk drive devices segments of data which have been modified while resident in the cache store and insures that space will be available in the cache store for new data if a particular operation requires that new data be transferred from a disk to the cache store for use. The subsystem may include plural storage control units and any of them may control the transfers of segments of data to the disks.

Abstract: A system for converting sequentially received data words, in the form of successively received groups of data words, into an interleaved output data word sequence, with each group of received data words consisting of T successive series of R data words. The system comprises N memories, each having W words locations, where W.multidot.N.gtoreq.T.multidot.R and where the N memories form a single memory matrix which is employed to process every group of received data words. Writing logic is provided for writing successively received data words of a first group of data words into the N memories in a predetermined sequence. Reading logic is provided for reading from the memories every R.sup.th data word of the first group of data words written into the to leave an available word location in each instance where a data word was read therefrom.

Abstract: In multiprocessor systems, and especially in multiprocessor emulation systems, time alignment between the individual processors is accomplished by using a time window established in a Local Pseudo-Time Accumulator (LPA) at each processor and a time reference hereinafter referred to as Master Pseudo Time (MPT). During the run time, any processor which is within the time frame of the window may continue execution. Any processor which falls behind the window must halt the advance of the Master Pseudo Time untl the processor can execute long enough to move back into the window. Any processor which moves ahead of the window must enter an idle state until the Master Pseudo Time advances enough for the processing element to move back into the window.

Abstract: A cache memory wherein data words identified by odd address numbers are stored separately from data words identified by even address numbers. A group of diagnostic control registers supply signals for controlling the testing of the cache within the cache memory to determine the operability of the individual elements included in the cache memory.

Abstract: A processor controlled automated mailing system for determining and printing the requisite postage for mailing an article includes a scale, a keyboard for operator input, a display and a meter setting device. After the requisite postage has been determined, a postage printing cycle is initiated by the operator. The processor determines whether the calculated postage value exceeds the digit printing capacity of the meter and, if so, advises the operator. The operator then determines if an entry error has been made and if not, reactivates the printing cycle. The processor thereafter initiates the meter setting device to sequentially print multiple tapes with each depression of the print key until the total value printed reaches the calculated postage value. An alternate embodiment incorporates a circuit for implementation of the method without processor control.

Abstract: A sequence block display system used with a programmable sequence controller for displaying a sequence block on a screen of a cathode-ray tube display unit in the form of ladder diagram. The sequence block display system is provided with a data processor and a buffer memory which includes first, second and third memories. The first memory is capable of storing the whole of sequence programs stored in the sequence controller and the second memory is capable of storing at least one sequence block. The third memory is adapted to store output instructions, which are used to designate a sequence block, in the same order as each designated sequence block is displayed on the screen and further to read out the output instructions in the reverse order for displaying the sequence blocks which are put out of the screen.