Patents Examined by Mark Tornow
  • Patent number: 10205010
    Abstract: A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 12, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toru Muramatsu, Hong-fei Lu, Haruo Nakazawa
  • Patent number: 10204682
    Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: February 12, 2019
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Eliodor G. Ghenciu, Thomas Rueckes, H. Montgomery Manning
  • Patent number: 10199217
    Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: February 5, 2019
    Assignee: Transphorm Inc.
    Inventors: Rongming Chu, Umesh Mishra, Rakesh K. Lal
  • Patent number: 10186614
    Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A semiconductor device comprising a first insulating layer, a first oxide semiconductor layer over the first insulating layer, a second oxide semiconductor layer over the first oxide semiconductor layer, a source electrode layer and a drain electrode layer over the second oxide semiconductor layer, a second insulating layer over the first insulating layer, the source electrode layer, and the drain electrode layer, a third insulating layer over the second insulating layer, a third oxide semiconductor layer over the second oxide semiconductor layer, a gate insulating layer over the third oxide semiconductor, and a gate electrode layer over the gate insulating layer. The second insulating layer is an oxygen barrier layer and includes a region in contact with side surfaces of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: January 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 10181580
    Abstract: An organic EL display device 1 includes a flexible plastic substrate 10, an organic EL element 4 on the plastic substrate 10, and to sealing film 2 provided on the plastic substrate 10 to cover the organic EL element 4. The sealing film 2 includes a first sealing layer 25 on a surface of the plastic substrate 10, a stress relief layer 26 on a surface of the first sealing layer 25, and a second sealing layer 27 on a surface of the stress relief layer 26. Compressive stress of the first sealing layer 25 is lower than compressive stress of the second sealing layer 27.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: January 15, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Mamoru Ishida, Kazuhiko Tsuda, Yoshifumi Ohta
  • Patent number: 10177304
    Abstract: Methods of forming a high sensitivity Hall effect sensor having a thin Hall plate and the resulting devices are provided. Embodiments include providing a SOI substrate having a sequentially formed Si substrate and BOX and Si layers; forming a first STI structure in a first portion of the Si layer above the BOX layer, the first STI structure having a cross-shaped pattern; forming a second STI structure in a frame-shaped pattern in a second portion of the Si layer; the second STI structure formed outside and adjacent to the first STI structure; removing a portion of the Si layer between the first and second STI structures down to the BOX layer; removing the first STI structure, a cross-shaped Si layer remaining; and implanting N+ dopant ions into each end of the cross-shaped Si layer to form N+ implantation regions.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: January 8, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10177123
    Abstract: A backplane optionally having stepped horizontal surfaces and optionally embedding metal interconnect structures is provided. First conductive bonding structures are formed on first stepped horizontal surfaces. First light emitting devices on a first transfer substrate are disposed on the first conductive bonding structures, and a first subset of the first light emitting devices is bonded to the first conductive bonding structures. Laser irradiation can be employed to selectively disconnect the first subset of the first light emitting devices from the first transfer substrate while a second subset of the first light emitting devices remains attached to the first transfer substrate.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 8, 2019
    Assignee: GLO AB
    Inventors: Nathan Gardner, Fredrick A. Kish, Jr., Miljenko Modric, Anusha Pokhriyal, Daniel Bryce Thompson, Fariba Danesh, Sharon N. Farrens
  • Patent number: 10170553
    Abstract: Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Renata Camillo-Castillo, Qizhi Liu, John J. Pekarik
  • Patent number: 10170687
    Abstract: The disclosed technology relates generally to magnetic devices, and more particularly to spin torque majority gate devices such as spin torque magnetic devices (STMG), and to methods of fabricating the same. In one aspect, a majority gate device includes a plurality of input zones and an output zone. A magnetic tunneling junction (MTJ) is formed in each of the input zones and the output zone, where the MTJ includes a non-magnetic layer interposed between a free layer stack and a hard layer. The free layer stack in turn includes a bulk perpendicular magnetic anisotropy (PMA) layer on a seed layer, a magnetic layer formed on and in contact with the bulk PMA layer, and a non-magnetic layer formed on the magnetic layer. Each of the bulk PMA layer and the seed layer is configured as a common layer for each of the input zones and the output zone.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: January 1, 2019
    Assignee: IMEC vzw
    Inventors: Johan Swerts, Mauricio Manfrini, Christoph Adelmann
  • Patent number: 10163857
    Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Jui-Pin Hung
  • Patent number: 10163878
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate. A method for manufacturing a semiconductor structure is also disclosed.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsing-Chih Lin, Ching-Chun Wang
  • Patent number: 10163975
    Abstract: A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at least one semiconductor light emitting device disposed on the top surface of the light-transmissive substrate, a reflective part disposed over the semiconductor light emitting device to reflect light from the semiconductor light emitting device toward the light-transmissive substrate, and a first wavelength converter disposed between the light-transmissive substrate and the reflective part.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: December 25, 2018
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Hyuck Jung Choi
  • Patent number: 10156335
    Abstract: A light-emitting device comprises a semiconductor structure comprising a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, a first intermediate layer, a second intermediate layer, and an active region capable of emitting radiation, wherein the active region is between the first intermediate layer and the second intermediate layer, the first intermediate layer is in direct contact with the first conductivity-type semiconductor layer, the second intermediate layer is in direct contact with the second conductivity-type semiconductor layer, and the active region comprises alternated well layers and barrier layers, wherein each barrier layer has a thickness; wherein a first difference between a refractive index of the first intermediate layer and a refractive index of the first conductivity-type semiconductor layer is less than a second difference between a refractive index of the second intermediate layer and a refractive index of the second conductivity-type semiconduct
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 18, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Jun-Yi Li, Chun-Yu Lin, Shih-Chang Lee, Yi-Ming Chen
  • Patent number: 10153315
    Abstract: A photosensitive imaging apparatus and a method of forming such an apparatus are disclosed. The apparatus includes: a first semiconductor substrate, including a photosensitive semiconductor layer including an array of photodetectors; and a second semiconductor substrate, stacked with the first semiconductor substrate and including a pixel-circuitry semiconductor layer including an array of in-pixel amplifier circuitries. Each in-pixel amplifier circuitry includes at least one first pixel MOS transistor. Each first pixel MOS transistor has an active region disposed between the gate layer thereof and the first semiconductor substrate. The photosensitive imaging apparatus allows an effective reduction in noises produced during light reception of the in-pixel amplifier circuitries and an increased light utilization of the photodetectors.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: December 11, 2018
    Assignee: SHANGHAI JADIC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jianhong Mao, Cheng Xu
  • Patent number: 10147732
    Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 4, 2018
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi Hu, Zhenyu Lu, Qian Tao, Jun Chen, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 10147777
    Abstract: A display device includes: a circuit part including at least one first region and at least one second region disposed adjacent to the first region, wherein the second region includes first pixel circuits arranged adjacent to the first region and second pixel circuits spaced apart from the first region; a display element part disposed on the circuit part, wherein a first display elements are connected to the first pixel circuits and overlap with the first region, and a second display elements are connected to the second pixel circuits; and bridge patterns electrically connecting the first and second pixel circuits and the first and second display elements, wherein the length of bridge patterns connecting the first pixel circuits and the first display elements is different from that of bridge patterns connecting the second pixel circuits and the second display elements.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 4, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bek Hyun Lim, Ki Nyeng Kang, Jin Koo Kang, Sun Kwang Kim
  • Patent number: 10141397
    Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Ichimura, Satoshi Eguchi, Tetsuya Iida, Yuya Abiko
  • Patent number: 10141373
    Abstract: A plurality of first conductive patterns is disposed on a substrate. Each of the plurality of first conductive patterns extends in a first direction. A first selection pattern is disposed on each of the plurality of first conductive patterns. A first barrier portion surrounds the first selection pattern. A first electrode and a first variable resistance pattern are disposed on the first selection pattern. A plurality of second conductive patterns is disposed on the first variable resistance pattern. Each of the plurality of second conductive patterns extends in a second direction crossing the first direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Song-Yi Kim, Jae-Kyu Lee, Dae-Hwan Kang, Gwan-Hyeob Koh
  • Patent number: 10134840
    Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 20, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Chun-Chen Yeh, Xiuyu Cai, Qing Liu, Ruilong Xie
  • Patent number: 10128149
    Abstract: Provided is a highly reliable semiconductor device and a method for manufacturing same. The method for manufacturing the semiconductor device includes forming an interlayer insulating film on a semiconductor substrate, forming a conductive plug in the interlayer insulating film, the conductive plug having a top surface for forming the same plane as the top surface of the interlayer insulating film, forming a first titanium film on the interlayer insulating film and the conductive plug, forming an aluminum diffusion-preventing film on the first titanium film, forming a second titanium film on the aluminum diffusion-preventing film, forming an aluminum film on the second titanium film, and shaping the area from the aluminum film to the first titanium film by etching to form wiring.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: November 13, 2018
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Takashi Kansaku