Abstract: Provided are a display substrate and a manufacturing method therefor, and a display device. The display substrate includes: a base substrate, a pixel defining layer (40, 40?) formed on the base substrate, and a light emitting layer located in a sub-pixel region (P) defined by the pixel defining layer (40, 40?), wherein, the pixel defining layer (40, 40?) includes: a reflecting layer (41, 41?), configured such that light emitted from the light emitting layer to the reflective layer (41, 41?) is reflected to a light outgoing side of the display substrate. The display device adopting the display substrate not only can effectively solve the problems of light leakage and light color interference, but also can effectively improve light out-coupling efficiency and color purity.

Abstract: The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide film. A semiconductor film over which a cap film is formed is irradiated with a laser to be crystallized under the predetermined condition, so that a crystalline semiconductor film including large grain crystals in which orientation of crystal planes is controlled in one direction is formed. The crystalline semiconductor film is used for silicide, whereby a uniform silicide film can be formed.

Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

Abstract: A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.

Abstract: A light emitting display device includes: a first substrate; a plurality of pixels arranged on the first substrate in a matrix and divided into a plurality of unit pixels arranged in a row direction and in a column direction, each of the unit pixels comprising a first pixel and a second pixel are arranged along the row direction, and a third pixel arranged in the column direction with respect to the first pixel and the second pixel; a first electrode corresponding to each of the pixels; a pixel defining layer partitioning the respective pixels on the substrate and having openings exposing the first electrode through the pixel defining layer; first light emitting layers consecutively on the first electrode of the first pixel and the second pixel of the unit pixels arranged in the same row line; second light emitting layers consecutively on the first electrode of the third pixel of the unit pixels arranged in the same row line; and a second electrode on the first light emitting layer and the second light emitti

Abstract: A light-emitting diode includes, a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer. The light-emitting diode also includes a transparent conductive layer including a first transparent conductive layer disposed on the second semiconductor layer and a second transparent conductive layer disposed on the first transparent conductive layer. The second transparent conductive layer has a conductivity different than the first transparent conductive layer.

Abstract: A display panel including pixels disposed on a substrate, where each of the pixels includes a light emitting element, and a capacitor. The capacitor of a first one of the pixels is partially overlapped, in a vertical direction, by respective pixel areas of two of the pixels. The anode of the capacitor of the first one of the pixels may be disposed closer to the substrate than a cathode of the capacitor, thereby reducing a parasitic capacitance between the capacitor and an anode of the light emitting element of one of the two pixels overlapping the capacitor.

Abstract: A light emitting device includes light emitting elements. A substrate includes electrically conductive layers each having a first region in which the light emitting elements are arranged and a second region connected to the first region and provided at a position higher than the first region. An electrically conductive wire electrically connects the light emitting elements arranged on the electrically conductive layer and the second region of the adjacent electrically conductive layer. A resin molded portion is formed of a light-transmissive resin that seals the light emitting elements and the electrically conductive wire. The resin molded portion has a shape in which centrally projected cylindrical lens portions is aligned, and in each of the cylindrical lens portions, the light emitting elements is arranged in a line shape. The second region is arranged between the light emitting elements in the light emitting element array.

Abstract: A method is presented for forming a semiconductor device. The method includes depositing a sacrificial layer on a fin structure formed on a substrate and then filled with polysilicon, etching a portion of the polysilicon material via a first etching process, and pre-cleaning the surface native oxide layer. The method further includes etching the remaining polysilicon material via a second etching process, and removing polysilicon etch residue formed adjacent the fin structure by a cleaning process. The pre-cleaning is performed by applying ammonia (NH3) and nitrogen trifluoride (NF3) or by applying buffered hydrofluoric acid (BHF). The first etching process is reactive ion etching (RIE) and the second etching process involves applying nitrogen trifluoride (NF3) and hydrogen gas (H2).

Abstract: A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.

Abstract: A thin film transistor and manufacturing and testing methods thereof, an array substrate and a display device, and the thin film transistor includes a semiconductor layer, at least three source/drain electrodes and a gate electrode. The semiconductor layer includes a non-doped part which is continuously formed and at least three doped parts which are connected with the non-doped part; the doped parts are spaced from each other and distributed at a periphery of the non-doped part; the source/drain electrodes are spaced from each other and respectively electrically connected with the doped parts; and the gate electrode overlaps the non-doped part in a direction perpendicular to the semiconductor layer and at least extends to a junction of the non-doped part and each doped part. The thin film transistor can improve the accuracy of comparison results of the characteristics of sub-thin film transistors included by the thin film transistor.

Abstract: A wiring substrate includes a first connection terminal and a protective insulation layer. The first connection terminal is electrically connected to a wiring layer by a via wiring and projects upward from an upper surface of an insulation layer. The protective insulation layer is located on the upper surface of the insulation layer to contact and cover a portion of a side surface of the first connection terminal. The first connection terminal includes a lower portion that is continuous with the via wiring and an upper portion that is continuous with the lower portion. The lower portion is smaller in crystal grain size than the upper portion. The lower portion and the upper portion are formed from the same metal material. The side surface of the lower portion has a higher roughness degree than the side surface of the upper portion.

Abstract: A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer.

Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first and second cut fin, the first cut fin having a first and second fin end and the second cut fin having a first and second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.

Abstract: A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first insulating layer is formed over a first surface of the encapsulant and an active surface of the semiconductor die. A second insulating layer is formed over a second surface of the encapsulant opposite the first surface. A conductive layer is formed over the first insulating layer. The conductive layer includes a line-pitch or line-spacing of less than 5 ?m. The active surface of the semiconductor die is recessed within the encapsulant. A third insulating layer is formed over the semiconductor die including a surface of the third insulating layer coplanar with a surface of the encapsulant. The second insulating layer is formed prior to forming the conductive layer. A trench is formed in the first insulating layer. The conductive layer is formed within the trench.

Abstract: A method of manufacturing an electronic device, comprising fixing a first wafer on a second wafer to form a space theirbetween, via a surrounding member configured to surround the space, forming an opening on a bottom side of the first wafer to expose a conductive member included in the first wafer, and then forming an electrode connected to the conductive member, wherein, in the fixing, the first wafer includes a trench intersecting the surrounding member, on an upper side of the first surface, and, in the forming, the electrode is formed under a condition that the space communicates with an external space via the trench.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first dielectric layer is formed on the substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the second dielectric layer is removed to form a contact hole, and a lateral etching process is conducted to expand the contact hole to form a funnel-shaped opening. Next, a metal layer is formed in the funnel-shaped opening, and the metal layer is planarized to form a second conductor.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.

Abstract: A method for manufacturing a semiconductor device comprises forming a silicide region on a semiconductor substrate, forming a gate structure on the semiconductor substrate adjacent the silicide region, forming a dielectric layer on the gate structure and on the silicide region, forming a first liner layer on the dielectric layer, removing a portion of the first liner layer and a portion of the dielectric layer to form an opening exposing a top surface of the silicide region, forming a second liner layer on the first liner layer and on sides and a bottom of the opening, removing a portion of the second liner layer from a top surface of the first liner layer and from the bottom of the opening to re-expose a portion of the top surface of the silicide region, and forming a contact layer in the opening directly on the re-exposed portion of the top surface of the silicide region.