Abstract: A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

Abstract: An epitaxial grown avalanche photodiode (APD), the avalanche photodiode comprising an anode, a cathode, an absorber, and a doped multiplier. The absorber and the doped multiplier are about between the cathode and the anode. The doped multiplier has a multiplier dopant concentration. The doped multiplier substantially depleted during operation of the epitaxial grown photodiode. The doped multiplier may comprise of a plurality of multiplication regions, each of the multiplication regions substantially depleted during operation of the avalanche photodiode.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region having a logic device disposed over a substrate and including a first metal gate disposed over a first high-k gate dielectric layer and an embedded memory region disposed adjacent to the logic region. The embedded memory region has a split gate flash memory cell including a select gate and a control gate. The control gate or the select gate is a metal gate separated from the substrate by a second high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes.

Abstract: A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.

Abstract: A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at least one semiconductor light emitting device disposed on the top surface of the light-transmissive substrate, a reflective part disposed over the semiconductor light emitting device to reflect light from the semiconductor light emitting device toward the light-transmissive substrate, and a first wavelength converter disposed between the light-transmissive substrate and the reflective part.

Abstract: An oxide semiconductor transistor used in a pixel element of a display device and a method of manufacturing the same are disclosed. The oxide semiconductor transistor used in a pixel element of a display device comprises a substrate, a first gate electrode located on the substrate, a source electrode and a drain electrode located on the first gate electrode and a second gate electrode located on the source electrode and the drain electrode. Here, the first gate electrode is electrically connected to the second gate electrode, the same voltage is applied to the first gate electrode and the second gate electrode, and a width of the second gate electrode is shorter than a length between the source electrode and the drain electrode.

Abstract: A method of producing a plurality of optoelectronic semiconductor chips includes a) providing a layer composite assembly having a principal plane which delimits the layer composite assembly in a vertical direction, and includes a semiconductor layer sequence having an active region that generates and/or detects radiation, wherein a plurality of recesses extending from the principal plane in a direction of the active region are formed in the layer composite assembly; b) forming a planarization layer on the principal plane such that the recesses are at least partly filled with material of the planarization layer; c) at least regionally removing material of the planarization layer to level the planarization layer; and d) completing the semiconductor chips, wherein for each semiconductor chip at least one semiconductor body emerges from the semiconductor layer sequence.

Abstract: A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.

Abstract: A method and structure for an electrical device and a plurality of electrical circuits including a plurality of carbon nanotubes (CNTs). The method can include forming a first CNT catalyst layer including a plurality of first CNT catalyst plugs, a plurality of electrical circuits electrically coupled to the first CNT catalyst layer, and a second CNT catalyst layer including a plurality of second CNT catalyst plugs electrically coupled to the second CNT catalyst layer. CNTs may be simultaneously formed on the plurality of first and second CNT catalyst plugs within a chemical vapor deposition (CVD) furnace.

Abstract: An inorganic-light-emitter display includes a display substrate and a plurality of spatially separated inorganic light emitters distributed on the display substrate in a light-emitter layer. A light-absorbing layer located on the display substrate in the light-emitter layer is in contact with the inorganic light emitters. Among other things, the disclosed technology provides improved angular image quality by avoiding parallax between the light emitters and the light-absorbing material, increased light-output efficiency by removing the light-absorbing material from the optical path, improved contrast by increasing the light-absorbing area of the display substrate, and a reduced manufacturing cost in a mechanically and environmentally robust structure using micro transfer printing.

Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

Abstract: Memory-opening semiconductor material portions and support opening fill structures can be simultaneously formed through a first alternating stack of first insulating layers and first sacrificial material layers. Dopant species that retard or prevent etching of the material of the support opening fill structures can be implanted into an upper portion of each support opening fill structure, while memory-opening semiconductor material portions are masked from implantation. After formation of a second alternating stack and second openings therethrough, the sacrificial material of the memory-opening semiconductor material portions is removed while the support opening fill structures is not removed. Damage to the first sacrificial material layers during formation of the staircase contact region and resulting leakage paths from word lines to the substrate through support pillar structures can be avoided or reduced by not removing the support opening fill structures.

Abstract: A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate. The portion of the semiconductor substrate has a (111) surface and a bottom surface. The (111) surface is slanted and has a top edge and a bottom edge. The bottom surface is parallel to a top surface of the insulation regions, and is connected to the bottom edge. A semiconductor region overlaps the portion of the semiconductor substrate, wherein the semiconductor region includes a second semiconductor material different from the first semiconductor material. The top edge and the bottom edge of the (111) surface are at a first depth and a second depth, respectively, relative to a top surface of the semiconductor region. A ratio of the first depth to the second depth is smaller than about 0.6.

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Abstract: System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling and may have an anti-oxidation coating. The interconnect may be attached to mounting pads on the top and bottom packages via an electrically conductive adhesive, including, but not limited to solder and solder paste. A solder preservative or other anti-oxidation coating may be applied to the mounting pad. A package-on-package assembly with solid interconnects may have a top package configured to accept at least one electronic device, with the solid interconnects mounted between the top package and a bottom package to rigidly hold the package about parallel to each other.

Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.

Abstract: The light emitting device is manufactured by processing that includes forming encapsulating member at least on the upper surface and upper surface perimeter of a light emitting element, removing at least the part of the encapsulating member that is on upper surface of the light emitting element and form a cavity with a perimeter that surrounds the light emitting element, and forming a wavelength-conversion layer inside the cavity to convert the wavelength of light emitted from the light emitting element.

Abstract: A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.