Patents Examined by Mark Tornow
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Patent number: 9012982Abstract: A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.Type: GrantFiled: February 4, 2008Date of Patent: April 21, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Keun-Nam Kim, Makoto Yoshida, Chul Lee, Dong-Gun Park, Woun-Suck Yang
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Patent number: 9012311Abstract: In a method for producing a semiconductor body, impurities which act as recombination centers in the semiconductor body and form a recombination zone are introduced into the semiconductor body during the process of producing the semiconductor body. In a semiconductor component, comprising a semiconductor body having a front surface and an opposite rear surface, and also a recombination zone formed by impurities between the front and rear surfaces, wherein the impurities act as recombination centers, the surface state density at the front and rear surfaces of the semiconductor body is just as high as the surface state density at a front and rear surface of an identical semiconductor body without a recombination zone.Type: GrantFiled: July 10, 2008Date of Patent: April 21, 2015Assignee: Infineon Technologies Austria AGInventors: Frank Pfirsch, Hans-Joachim Schulze
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Patent number: 9006711Abstract: Disclosed is a white light-emitting organic electroluminescent device, which is excellent in stability of emission chromaticity over a long operation period, while having high electrical efficiency, long life, excellent storage stability and excellent color rendering properties. Also disclosed is an illuminating device using such an organic electroluminescent device. Specifically disclosed is an organic electroluminescent device having a light-emitting layer between an anode and a cathode, which is characterized by comprising a light-emitting layer A having a maximum emission wavelength of not more than 480 nm and containing a phosphorescent dopant having a maximum emission wavelength of not more than 480 nm, and a light-emitting layer B arranged between the light-emitting layer A and the anode, which has a maximum emission wavelength of not less than 510 nm and contains a phosphorescent dopant.Type: GrantFiled: April 4, 2008Date of Patent: April 14, 2015Assignee: Konica Minolta Holdings, Inc.Inventors: Yoriko Nakayama, Tomoyuki Nakayama, Kunimasa Hiyama, Shigeru Kojima
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Patent number: 8999801Abstract: A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.Type: GrantFiled: September 19, 2011Date of Patent: April 7, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kensuke Ota, Masumi Saitoh, Toshinori Numata
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Patent number: 8999836Abstract: It is an object of the present invention to provide a technique for manufacturing a highly reliable display device at low cost with high yield. A first electrode layer is formed by a sputtering method using a gas containing hydrogen or H2O, an electroluminescent layer is formed over the first electrode layer, and a second electrode layer is formed over the electroluminescent layer. According to one aspect of the present invention, a display device is manufactured to include a first electrode layer including indium zinc oxide containing silicon oxide and tungsten oxide, an electroluminescent layer over the first electrode layer, and a second electrode layer over the electroluminescent layer, where the electroluminescent layer includes a layer containing an organic compound and an inorganic compound to be in contact with the first electrode layer.Type: GrantFiled: May 9, 2006Date of Patent: April 7, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiaki Oikawa, Kengo Akimoto
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Patent number: 8994142Abstract: The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.Type: GrantFiled: April 4, 2012Date of Patent: March 31, 2015Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Maud Vinet, Laurent Grenouillet, Yannick Le Tiec, Nicolas Posseme
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Patent number: 8994094Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked body, first and second semiconductor pillars, a connecting portion, a first memory film, and a dividing portion. The stacked bodies include a plurality of electrode films stacked along a first axis and as interelectrode insulating film provided between the electrode films. The first and second semiconductor pillars penetrate through the first and second stacked bodies along the first axis, respectively. The connecting portion electrically connects the first and second semiconductor pillars. The first memory film is provided between the electrode film and the semiconductor pillar. The dividing portion electrically divides the first and second electrode films from each other between the first semiconductor pillar and the second semiconductor pillar, is in contact with the connecting portion, and includes a stacked film including a material used for the first memory film.Type: GrantFiled: September 18, 2011Date of Patent: March 31, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Toru Matsuda
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Patent number: 8980730Abstract: Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially-single-particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.Type: GrantFiled: September 14, 2011Date of Patent: March 17, 2015Assignee: STC.UNMInventors: Seung-Chang Lee, Steven R. J. Brueck
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Patent number: 8981349Abstract: An organic light emitting diode display device constructed with an organic light emitting element including a first electrode, an organic emission layer, and a second electrode sequentially laminated together, a transmittance control layer formed on the organic light emitting element, a selective reflective layer formed on the transmittance control layer, a polarizing plate formed on the selective reflective layer, and a phase retardation plate disposed between the organic light emitting element and the polarizing plate.Type: GrantFiled: December 18, 2009Date of Patent: March 17, 2015Assignee: Samsung Display Co., Ltd.Inventors: Soon-Ryong Park, Hee-Seong Jeong, Woo-Suk Jung, Jae-Yong Kim, Joo-Hwa Lee, Chul-Woo Jeong, Hee-Chul Jeon, Eun-Ah Kim, Noh-Min Kwak
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Patent number: 8981577Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an interposer having an interposer first side and an interposer second side opposing the interposer first side; mounting an integrated circuit to the interposer first side, the integrated circuit having a non-active side and an active side with the non-active side facing the interposer; connecting first interconnects between the active side and the interposer first side, the first interconnects having a first density on the interposer first side; mounting the interposer over a package carrier with the interposer first side facing the package carrier; connecting second interconnects between the package carrier and the interposer second side, the second interconnects having a second density on the interposer second side, the second density that is approximately the same as the first density; and forming an encapsulation over the package carrier covering the interposer and the second interconnects.Type: GrantFiled: March 24, 2010Date of Patent: March 17, 2015Assignee: STATS ChipPAC Ltd.Inventor: Mukul Joshi
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Patent number: 8957448Abstract: An LED package and method thereof include an insulation plate, and a metal board disposed on the insulation plate and etched to form a cavity, wherein the metal board is etched to partially expose the insulation plate to form the cavity. The LED package and method also include an LED chip configured to be mounted inside the cavity, and an encapsulation member filling the cavity, wherein the encapsulation member comprises an epoxy resin. The LED package and method include a through-hole configured to be formed on the insulation plate where the LED chip is mounted. The through-hole enables portions of the LED chip to be exposed, and a metal configured to fill the through-hole to form an electrode to be electrically connected to the LED chip.Type: GrantFiled: March 29, 2012Date of Patent: February 17, 2015Assignee: Sungkyunkwan University Foundation for Corporate CollaborationInventors: Su Jeong Suh, Haw Sun Park
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Patent number: 8946764Abstract: A GaN-based semiconductor element which can suppress a leakage current generated during reverse bias application, an optical device using the same, and an image display apparatus using the optical device are provided. The GaN-based semiconductor element has a first GaN-based compound layer including an n-type conductive layer; a second GaN-based compound layer including a p-type conductive layer; and an active layer provided between the first GaN-based compound layer and the second GaN-based compound layer. In this GaN-based semiconductor element, the first GaN-based compound layer includes an underlayer having an n-type impurity concentration in the range of 3×1018 to 3×1019/cm3, and when a reverse bias of 5 V is applied, a leakage current density, which is the density of a current flowing per unit area of the active layer, is 2×10?5 A/cm2 or less.Type: GrantFiled: June 12, 2008Date of Patent: February 3, 2015Assignee: Sony CorporationInventors: Goshi Biwa, Ippei Nishinaka, Hiroyuki Okuyama
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Patent number: 8940572Abstract: A conductive contact pattern is formed on a surface of solar cell by forming a thin conductive layer over at least one lower layer of the solar cell, and ablating a majority of the thin conductive layer using a laser beam, thereby leaving behind the conductive contact pattern. The laser has a top-hat profile, enabling precision while scanning and ablating the thin layer across the surface. Heterocontact patterns are also similarly formed.Type: GrantFiled: April 21, 2010Date of Patent: January 27, 2015Assignee: Tetrasun, Inc.Inventor: Adrian Turner
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Patent number: 8936996Abstract: A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.Type: GrantFiled: December 2, 2010Date of Patent: January 20, 2015Assignee: International Business Machines CorporationInventors: Ravi M. Todi, Joseph Ervin, Chengwen Pei, Geng Wang
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Patent number: 8928059Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.Type: GrantFiled: September 6, 2012Date of Patent: January 6, 2015Assignee: SK Hynix Inc.Inventors: Sung-Jin Whang, Dong-Sun Sheen, Seung-Ho Pyi, Min-Soo Kim
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Patent number: 8927970Abstract: An organic electroluminescence device and a method for manufacturing the same are disclosed. The organic electroluminescence device includes a transparent substrate, a semiconductor layer including a source region, a channel region and a drain region, a gate insulating film having first contact holes on the source and drain regions and formed on the substrate including the semiconductor layer, a gate electrode formed on the gate insulating film above the channel region, an interlayer insulating film having second contact holes on the source and drain regions and formed on an entire surface of the gate insulating film including the gate electrode, and a source electrode and a drain electrode formed on the interlayer insulating film to be electrically connected to the source and drain regions through the first and second contact holes, wherein at least one of the source electrode and the drain electrode is formed to cover the semiconductor layer.Type: GrantFiled: September 12, 2008Date of Patent: January 6, 2015Assignee: LG Display Co., Ltd.Inventors: Yun Sik Jeong, Joon Young Heo
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Patent number: 8921865Abstract: A display panel including pixels disposed on a substrate, where each of the pixels includes a light emitting element, and a capacitor. The capacitor of a first one of the pixels is partially overlapped, in a vertical direction, by respective pixel areas of two of the pixels. The anode of the capacitor of the first one of the pixels may be disposed closer to the substrate than a cathode of the capacitor, thereby reducing a parasitic capacitance between the capacitor and an anode of the light emitting element of one of the two pixels overlapping the capacitor.Type: GrantFiled: November 29, 2012Date of Patent: December 30, 2014Assignee: Sony CorporationInventors: Mitsuru Asano, Yukihito Iida
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Patent number: 8916958Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, a first substrate, a second substrate and a metal cap. The chips are electrically connected to the first substrate, the second substrate is disposed between the chips, and the chips and the second substrate are disposed within the metal cap.Type: GrantFiled: April 24, 2009Date of Patent: December 23, 2014Assignee: Infineon Technologies AGInventors: Chong Yee Tong, Hui Teng Wang
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Patent number: 8912632Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity type base layer, a second conductivity type base layer, a first conductivity type second semiconductor layer, a gate insulating film, a gate electrode, and a second major electrode. The gate insulating film is provided on a side wall of a trench penetrating the second conductivity type base layer to reach the first conductivity type base layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and electrically connected with the second semiconductor layer. A maximum impurity concentration in the second semiconductor layer is within ten times a maximum impurity concentration in the second conductivity type base layer.Type: GrantFiled: September 15, 2011Date of Patent: December 16, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Tsuneo Ogura
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Patent number: 8901584Abstract: A light emitting diode including a compound semiconductor layer having at least a pn junction-type light emitting unit and a strain adjustment layer stacked on the light emitting unit, wherein the light emitting unit has a stacked structure containing a strained light emitting layer having a composition formula of (AlXGa1-X)YIn1-YP (wherein X and Y are numerical values that satisfy 0?X?0.1 and 0.39?Y?0.45 respectively) and a barrier layer, and the strain adjustment layer is transparent to the emission wavelength and has a lattice constant that is smaller than the lattice constants of the strained light emitting layer and the barrier layer. The light emitting diode has an emission wavelength of not less than 655 nm, exhibits excellent monochromaticity, high output and/or high efficiency, and has a fast response speed.Type: GrantFiled: March 3, 2010Date of Patent: December 2, 2014Assignee: Showa Denko K.K.Inventors: Noriyoshi Seo, Atsushi Matsumura, Ryouichi Takeuchi