Abstract: A photoelectric device includes an electrode structure, an LED (light emitting diode) element, a zener diode and a reflective cup. The LED element, the zener diode and the reflective cup are arranged on the electrode structure. The LED element and the zener diode are electrically connected in anti-parallel with each other. The reflective cup comprises an inner surface defined thereof and a nick defined in an outside of the reflective cup. The LED element is surrounded by the inner surface of the reflective cup and the zener diode is arranged in the nick.

Abstract: A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer.

Abstract: The present disclosure relates to a method for performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a first cut layer over a substrate having a multi-layer hard mask with a first layer and an underlying second layer. A first plurality of openings, cut according to the first cut layer, are formed to expose the second layer at a first plurality of positions corresponding to a first plurality of shapes of a SALE design layer. A spacer material is deposited onto sidewalls of the multi-layer hard mask to form a second cut layer. A second plurality of openings, cut according to the second cut layer, are formed to expose the second layer at a second plurality of positions corresponding to a second plurality of shapes of the SALE design layer. The second layer is etched according to the first and second plurality of openings.

Abstract: A semiconductor device includes an interlayer insulating film; a wiring formed on the interlayer insulating film so as to protrude there from and made of a material having copper as a main component, the wiring having a thickness direction and having a cross sectional shape of an inverted trapezoid that becomes wider in width with distance away from the interlayer insulating film; and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material differing from those of the first and second nitride films, and has a tapered portion having a cross sectional shape of a trapezoid that becomes narrower in width with distance away from the interlayer insulating film.

Abstract: For a photosensor, an array substrate is provided, wherein the edge of a photodiode is enclosed by the opening edge of a contact hole formed on a drain electrode.

Abstract: A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.

Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.

Abstract: It is an object of the present invention to provide a technique for manufacturing a highly reliable display device at low cost with high yield. A first electrode layer is formed by a sputtering method using a gas containing hydrogen or H2O, an electroluminescent layer is formed over the first electrode layer, and a second electrode layer is formed over the electroluminescent layer. According to one aspect of the present invention, a display device is manufactured to include a first electrode layer including indium zinc oxide containing silicon oxide and tungsten oxide, an electroluminescent layer over the first electrode layer, and a second electrode layer over the electroluminescent layer, where the electroluminescent layer includes a layer containing an organic compound and an inorganic compound to be in contact with the first electrode layer.

Abstract: A phase change memory with a heater with sublithographic dimensions may be achieved, in some embodiments, with lower thermal budget. The phase change memory may use a controlled etching process to reduce the lateral dimension of the heater.

Abstract: Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are formed from a core material of the interposer, such that the interposer may absorb thermally induced stresses and conform to warped or uneven surfaces. Embodiments of electronic device packages including a semiconductor die mounted to and electrically connected to the interposer, as well as methods for forming the electronic device packages, are also disclosed. In one electronic device package, the semiconductor die is electrically connected to the interposer with wire bonds attached to a routing layer of the interposer. In another electronic device package, the semiconductor die is electrically connected to the interposer by bonding the semiconductor die to the flexible solder pad elements of the interposer in a flip-chip configuration.

Abstract: To provide a substrate which is light and has high reliability and high light extraction efficiency from an organic EL element. To provide a substrate which includes a protective layer in a resin layer, an uneven structure on a light incident surface, and an opening which surrounds the uneven structure and through which the protective layer is exposed. To provide a light-emitting device which includes a resin layer provided with an uneven structure on a light incident surface over a protective layer, and a light-emitting element in the protective layer and a counter substrate which are bonded with a sealant. The protective layer and the resin layer have a property of transmitting visible light. The light-emitting element includes a light-transmitting first electrode over a resin layer, a layer containing a light-transmitting organic compound over the first electrode, and a second electrode over the layer containing a light-transmitting organic compound.

Abstract: A spin transport device includes a semiconductor layer 3, a first ferromagnetic layer 1 provided on the semiconductor layer 3 via a first tunnel barrier layer 5A, and a second ferromagnetic layer 2 provided on the semiconductor layer 3 via a second tunnel barrier layer 5B to be spaced from the first ferromagnetic layer 1, and the semiconductor layer 3 includes a first region RI broadening in a direction away from the first ferromagnetic layer 1 along a direction orthogonal to a thickness direction from the first ferromagnetic layer 1, and a second region R12 extending in a direction toward the second ferromagnetic layer 2 along the direction orthogonal to the thickness direction from the first ferromagnetic layer 1. The second region R12 has a relatively higher impurity concentration than the first region R1.

Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.

Abstract: A process for producing a thin film field-effect transistor includes providing a gate electrode, a gate insulating film, and source and drain electrodes, treating entire surfaces of the source and drain electrodes with a mixture of sulfuric acid and hydrogen peroxide, and providing an organic electronic material layer containing an organic electronic material on the gate insulating film to be in electrical contact with the source and drain electrodes. A reaction product of the organic electronic material, sulfuric acid and hydrogen peroxide containing a sulfonated product of the organic electronic material is present only at an interface between the source electrode and the organic electronic material layer and an interface between the drain electrode and the organic electronic material layer to thereby increase the electroconductivity of the organic electronic material and reduce a charge injection barrier from the source electrode to the organic electronic material.

Abstract: In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors.

Abstract: A vertical transistor has a first air-gap spacer between the gate and the bottom source/drain, and a second air-gap spacer between the gate and the contact to the bottom source/drain. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

Abstract: A display panel including pixels disposed on a substrate, where each of the pixels includes a light emitting element, and a capacitor. The capacitor of a first one of the pixels is partially overlapped, in a vertical direction, by respective pixel areas of two of the pixels. The anode of the capacitor of the first one of the pixels may be disposed closer to the substrate than a cathode of the capacitor, thereby reducing a parasitic capacitance between the capacitor and an anode of the light emitting element of one of the two pixels overlapping the capacitor.

Abstract: An embodiment of an apparatus to reduce supply voltage noise with capacitors of an interposer of a stacked die is disclosed. In this embodiment, an interposer is coupled to a first integrated circuit die using a first plurality of interconnects. A substrate is coupled to the interposer using a second plurality of interconnects. The substrate includes a supply voltage plane and a ground plane, each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects. The interposer includes capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects, where capacitance from capacitors of the interposer is provided to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate.

Abstract: The present invention provides a light emitting device, which comprises an epitaxial stack structure, a II/V group compound contact layer directly formed on the epitaxial stack structure, a protrusion or recess type structure directly formed on the II/V group compound contact layer, and a conductive layer covering the protrusion or recess type structure.

Abstract: A method for providing a semiconductor chip package with side wettable plating includes singulating a semiconductor chip package from an array of packages formed in a block format, immersing the semiconductor chip package in a bath of plating solution, contacting a lead land of the semiconductor chip package with conductive contact material within the bath of plating solution, connecting the conductive contact material to a cathode electrical potential, connecting an anode within the bath of plating solution to an anode electrical potential, and plating the lead land of the semiconductor chip package.