Abstract: Manipulation of the passivation ligands of colloidal quantum dots and use in QD electronics. A multi-step electrostatic process is described which creates bare QDs, followed by the formation of QD superlattice via electric and thermal stimulus. Colloidal QDs with original long ligands (i.e. oleic acid) are atomized, and loaded into a special designed tank to be washed, followed by another atomization step before entering the doping station. The final step is the deposition of bare QDs onto substrate and growth of QD superlattice. The method permits the formation of various photonic devices, such as single junction and tandem solar cells based on bare QD superlattice, photodetectors, and LEDs. The devices include a piezoelectric substrate with an electrode, and at least one layer of bare quantum dots comprising group IV-VI elements on the electrode, where the bare quantum dots have been stripped of outer-layer ligands.

Abstract: A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.

Abstract: A method for fabricating a semiconductor device includes forming, over a substrate, a plurality of first conductive structures which are separated from one another; forming multi-layered dielectric patterns including a first dielectric layer which covers upper ends and both sidewalls of the first conductive structures; removing portions of the first dielectric layer starting from lower end portions of the first conductive structures to define air gaps, and forming second conductive structures which are filled between the first conductive structures.

Abstract: A light-emitting element includes a light-emitting layer having a two-layer structure in which a first light-emitting layer containing a first light-emitting substance and a second light-emitting layer containing a second light-emitting substance, which is in contact with the first light-emitting layer, are provided between an anode and a cathode. The first light-emitting layer is separated into two layers of a layer provided on the anode side and a layer provided on the cathode side. The layer provided on the anode side contains only a first light-emitting substance, or a first organic compound of less than 50 wt % and the first light-emitting substance of 50 wt % to 100 wt %. The layer provided on the cathode side contains a second organic compound and the first light-emitting substance. The second light-emitting layer, which is provided in contact with the first light-emitting layer, contains the second light-emitting substance and a third organic compound.

Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

Abstract: First and second ranges of a silicon carbide film have an interface. The first range includes: a first breakdown voltage holding layer having a first conductivity type; and an outer edge embedded region provided at an interface in the outer edge portion and having a second conductivity type. The second range includes a second breakdown voltage holding layer having the first conductivity type. A semiconductor element is formed in the second range. The first range includes: a central section facing the semiconductor element in the central portion in a thickness direction; and an outer edge section facing the semiconductor element in the outer edge portion in the thickness direction. At the interface, the outer edge section includes a portion having an impurity concentration different from the impurity concentration of the central section.

Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.

Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode.

Abstract: An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation.

Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.

Abstract: Structures and methods for blocking ultraviolet rays during a film depositing process for semiconductor device are disclosed. In one embodiment, a semiconductor device includes an oxide-nitride-oxide (ONO) film formed on a semiconductor substrate, a gate electrode formed on the ONO film, a lower layer insulation film formed on the ONO film and the gate electrode, and a ultraviolet (UV) blocking layer based on a plurality of granular particles scattered in at least one insulation film formed on lower layer insulation film, where the UV blocking layer suppresses UV rays generated during an additional film deposition from reaching the ONO film.

Abstract: A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. Then, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.

Abstract: In a package process of backside illumination image sensor, a wafer including a plurality of pads is provided. A first carrier is processed to form a plurality of blind vias therein. The first carrier is adhered to the wafer so that the blind vias face to the pads correspondingly. A spacing layer is formed and a plurality of sensing components are disposed. A second carrier is adhered on the spacing layer. Subsequently, a carrier thinning process is performed so that the blind vias become the through holes. An insulating layer is formed on the first carrier. An electrically conductive layer is formed on the insulating layer and filled in the though holes to electrically connect to the pads. The package process can achieve the exact alignment of the through holes and the pads, thereby increasing the package efficiency and improving the package quality.

Abstract: Various embodiments provide non-planar nanowires, nanowire arrays, and nanowire networks as well as methods of their formation and applications. The non-planar nanowires and their arrays can be formed in a controlled manner on surfaces having a non-planar orientation. In embodiments, two or more adjacent nanowires from different surfaces can grow to merge together forming one or more nanowire branches and thus forming a nanowire network. In embodiments, the non-planar nanowires and nanowire networks can be used for cantilever oscillation, switching and transistor actions.

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract: Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

Abstract: Some exemplary embodiments of a III-nitride switching device with an emulated diode have been disclosed. One exemplary embodiment comprises a GaN switching device fabricated on a substrate comprising a high threshold GaN transistor coupled across a low threshold GaN transistor, wherein a gate and a source of the low threshold GaN transistor are shorted with an interconnect metal to function as a parallel diode in a reverse mode. The high threshold GaN transistor is configured to provide noise immunity for the GaN switching device when in a forward mode. The high threshold GaN transistor and the low threshold GaN transistor are typically fabricated on the same substrate, and with significantly different thresholds. As a result, the superior switching characteristics of III-nitride devices may be leveraged while retaining the functionality and the monolithic structure of the inherent body diode in traditional silicon FETs.

Abstract: A display device according to an exemplary embodiment of the present invention includes a display portion including a plurality of display pixels displaying an image and a dummy portion including a plurality of dummy pixels formed in a periphery region of the display portion. An electrostatic test element group (TEG) may be formed in at least one of the dummy pixels.

Abstract: The present invention relates generally to power switches for aircraft. According to a first aspect, the present invention provides an integrated solid state power switch for fault protection in an aircraft power distribution system. The integrated solid state power switch is formed of semiconductor material that provides a field effect transistor (FET) channel that is operable during normal device operation to provide an operating current flow path and a bipolar transistor channel that is operable during device overload conditions to provide an overload current flow path. A method for manufacturing such an integrated solid state power switch is also described. Various embodiments of the invention provide automatic overload current protection for aircraft systems without the need to use bulky switches or heavy cooling equipment.

Abstract: Some demonstrative embodiments include devices and/or methods of gettering on silicon on insulator (SOI) substrate. For example, a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) may include a plurality of pixels arranged on a wafer, a pixel of the pixels including: a silicon active area; at least one non-silicided leakage-sensitive component formed on the active area, the leakage-sensitive component is sensitive to metal contaminants; a non-leakage-sensitive area formed on the active area, the non-leakage-sensitive area surrounding the leakage-sensitive component; and at least one silicided gettering region formed on the non-leakage-sensitive area to trap the metal contaminants.