Patents Examined by Mark V. Prenty
  • Patent number: 11450712
    Abstract: A memristive device and mechanisms for providing and using the memristive device are described. The memristive device includes a nanowire, a plurality of memristive plugs and a plurality of electrodes. The nanowire has a conductive core and an insulator coating at least a portion of the conductive core. The insulator has a plurality of apertures therein. The memristive plugs are for the apertures. At least a portion of each of the memristive plugs resides in each of the apertures. The memristive plugs are between the conductive core and the electrodes.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 20, 2022
    Assignee: Rain Neuromorphics Inc.
    Inventors: Jack David Kendall, Suhas Kumar, Nikita Gaur
  • Patent number: 11450756
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: September 20, 2022
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
  • Patent number: 11444046
    Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Patent number: 11437572
    Abstract: Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: September 6, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Kil Su Jung, Keun Heo
  • Patent number: 11430948
    Abstract: A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 30, 2022
    Assignee: INTEL CORPORATION
    Inventors: Timothy Glassman, Dragos Seghete, Nathan Strutt, Namrata S. Asuri, Oleg Golonzka, Hiten Kothari, Matthew J. Andrus
  • Patent number: 11417678
    Abstract: Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: August 16, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Wen Hung, Yu-Kai Liao, Chiang-Hung Chen
  • Patent number: 11411024
    Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 9, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Yun Lee, Jae-Hoon Jang, Jae-Duk Lee, Joon-Hee Lee, Young-Jin Jung
  • Patent number: 11411113
    Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Hsiang Lin, Tai-Chun Huang, Tien-I Bao
  • Patent number: 11410877
    Abstract: Source/drain contact spacers for improving integrated circuit device performance and methods of forming such are disclosed herein. An exemplary method includes etching an interlayer dielectric (ILD) layer to form a source/drain contact opening that exposes a contact etch stop layer (CESL) disposed over a source/drain feature, depositing a source/drain contact spacer layer that partially fills the source/drain contact opening and covers the ILD layer and the exposed CESL, and etching the source/drain contact spacer layer and the CESL to extend the source/drain contact opening to expose the source/drain feature. The etching forms source/drain contact spacers. The method further includes forming a source/drain contact to the exposed source/drain feature in the extended source/drain contact opening. The source/drain contact is formed over the source/drain contact spacers and fills the extended source/drain contact opening.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Xusheng Wu
  • Patent number: 11404541
    Abstract: A HEMT comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; and a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the channel layer comprises: at least a first GaN layer; and a first graded AlGaN layer on the first GaN layer, the Al proportion of the first graded AlGaN layer increasing with the distance from the first GaN layer.
    Type: Grant
    Filed: July 11, 2020
    Date of Patent: August 2, 2022
    Assignee: HRL LABORATORIES, LLC
    Inventors: Jeong-sun Moon, Fevzi Arkun
  • Patent number: 11404324
    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng, Yen-Ming Chen
  • Patent number: 11393977
    Abstract: A semiconductor device is provided including a plurality of first conductive patterns disposed on a substrate. A first insulating pattern is disposed between the plurality of first conductive patterns. A plurality of second conductive patterns is disposed on the plurality of first conductive patterns. A first memory cell structure is disposed between the plurality of first conductive patterns and the plurality of second conductive patterns. A second insulating pattern is disposed on the first insulating pattern and on a side surface of the first memory cell structure. A first vertical structure is disposed on the first insulating pattern and passing through the second insulating pattern to an upper surface of the substrate. The first insulating pattern has a plurality of recess portions. The plurality of recess portions include a first recess portion and a second recess portion. The first recess portion and the second recess portion have different depths.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaeuk Shin, Youngtak Kim, Sangjine Park, Hyeyeong Seo, Wonjun Lee
  • Patent number: 11387369
    Abstract: An example apparatus includes forming a working surface of a substrate material. The example apparatus includes trench formed between two semiconductor structures on the working surface of the substrate material. The example apparatus further includes access lines formed on neighboring sidewalls of the semiconductor structures opposing a channel region separating a first source/drain region and a second source/drain region. The example apparatus further includes a time-control formed inhibitor material formed over a portion of the sidewalls of the semiconductor structures. The example apparatus further includes a dielectric material formed over the semiconductor structures to enclose a non-solid space between the access lines.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shen Hu, Hung-Wei Liu, Xiao Li, Zhiqiang Xie, Corey Staller, Jeffery B. Hull, Anish A. Khandekar, Thomas A. Figura
  • Patent number: 11387339
    Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same, and it relates to a field of semiconductor technology. The semiconductor device includes a substrate, a semiconductor layer, a dielectric layer, a source, a drain, and a gate, wherein a first face of the gate close to a side of the drain and close to the semiconductor layer has a first curved face. A gate trench corresponding to the gate is provided on the dielectric layer, a material of the gate being filled in the gate trench, and at least a part of a second face of the gate trench in contact with the gate is a second curved face which extends from a surface of the dielectric layer away from the semiconductor layer toward the semiconductor layer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 12, 2022
    Assignee: DYNAX SEMICONDUCTOR, INC.
    Inventors: Naiqian Zhang, Xi Song, Qingzhao Gu, Xingxing Wu
  • Patent number: 11365347
    Abstract: A method for preparation of perovskite quantum dot (PQD)/polymer/ceramic ternary complex includes encapsulation of bifunctional coating including ceramic and polymer. Encapsulation sequence of polymer and ceramic may be altered according to the application. In one scenario, the perovskite quantum dots may be protected with ceramic coating first and further coated with polymer to obtain the perovskite/ceramic/polymer ternary complex. In another scenario, the perovskite quantum dots may be protected with polymer coating first and followed by ceramic coating to obtain the perovskite/polymer/ceramic ternary complex. The PQD ternary complex may provide synergistic effect on improvement of stability towards heat and moisture when compared to existing technology.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: June 21, 2022
    Assignee: Nano and Advanced Materials Institute Limited
    Inventors: Chi Hin Wong, Wing Yin Yung, Sze Chun Yiu, Chi Ho Kwok, Chenmin Liu
  • Patent number: 11362275
    Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 14, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Nicolas Louis Gabriel Breil, Siddarth Krishnan, Shashank Sharma, Ria Someshwar, Kai Ng, Deepak Kamalanathan
  • Patent number: 11362274
    Abstract: A laterally switching cell structure including a metal-insulator-metal stack includes an active metal oxide layer including one or more sub-stoichiometric regions. The metal oxide layer includes one or more metal-oxides deposited conformally using a mixed precursor atomic layer deposition process. A graded oxygen profile in the metal oxide layer(s) of the stack including a mirrored impurity density may be formed wherein the sub-stoichiometric region(s) include a relatively high density of impurities obtained as reaction by-products. Arrays of cell structures can be formed with no requirement for a thick active electrode, allowing for more space for a metal fill and optional selector, thereby reducing access resistance.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: June 14, 2022
    Assignees: International Business Machines Corporation, ULVAC, INC.
    Inventors: John Rozen, Takashi Ando, Martin M. Frank, Yohei Ogawa
  • Patent number: 11361990
    Abstract: Provided are a substrate processing method and a device manufactured by using the same, which may improve etch selectivity of an insulating layer deposited on a stepped structure. The substrate processing method includes: forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface; weakening at least a portion of the first layer; forming a second layer on the first layer; and performing an isotropic etching process on the first layer and the second layer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: June 14, 2022
    Assignee: ASM IP Holding B.V.
    Inventor: Yoon Ki Min
  • Patent number: 11335730
    Abstract: A vertical resistive switching memory device is provided that includes a resistive random access memory (ReRAM) stack embedded in a material stack of alternating layers of an interlayer dielectric material and a recessed electrode material. A selector device encapsulates a portion of the ReRAM stack and is present in an undercut region that is laterally adjacent to each of the recessed electrode material layers of the material stack.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: May 17, 2022
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Praneet Adusumilli, Reinaldo Vega, Cheng Chi
  • Patent number: 11329123
    Abstract: An OLED display panel is provided which can control the problem of shedding even in high definition panels. Metal wiring 5 which conducts with an earth line of a flexible printed substrate 15 is provided on a substrate 1. A display area 2 comprised from a plurality of OLED elements is provided at the center of the substrate 1 and four low resistance metal films 3 are provided along each of four edges of the display area 2 on a surface of insulation films 8, 10 at the periphery of the display area 2. Among these, one low resistance metal film 3 conducts with the metal wiring 5 via a 3a.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 10, 2022
    Assignee: Japan Display Inc.
    Inventors: Kouhei Takahashi, Hirotsugu Sakamoto, Takeshi Ookawara, Toshihiro Sato