Patents Examined by Mark V. Prenty
  • Patent number: 10475905
    Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: November 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chi-Chun Liu, Chun Wing Yeung, Robin Hsin Kuo Chao, Zhenxing Bi, Kristin Schmidt, Yann Mignot
  • Patent number: 10475998
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bottom electrode having a first width and a dielectric structure having a second width formed over the bottom electrode. The semiconductor structure further includes a top electrode having a third width formed over the dielectric structure. In addition, the second width of the dielectric structure is greater than the first width of the bottom electrode.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
  • Patent number: 10475800
    Abstract: An IC is provided. The IC includes a plurality of P-type fin field-effect transistors (FinFETs). At least one first P-type FinFET includes a silicon germanium (SiGe) channel region. At least one second P-type FinFET includes a Si channel region. Source and drain regions of the plurality of P-type FinFETs include SiGe and a p-type impurity.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10461047
    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semi-conductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan, Sairam Agraharam
  • Patent number: 10446685
    Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Matthew V. Metz, Harold W. Kennel, Gilbert Dewey, Willy Rachmady, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10427935
    Abstract: A manufacturing method for a semiconductor structure is disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 1, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
  • Patent number: 10431520
    Abstract: A space having a certain thickness is provided between a metal base and a heat-dissipation fin set or the like. A semiconductor device is provided, including: a package portion; a metal base which is housed in the package portion and is exposed at a lower surface of the package portion; a semiconductor chip which is housed in the package portion and is placed above the metal base; and a frame portion provided to surround a penetration space penetrating the package portion, wherein a lower end of the frame portion protrudes below the lower surface of the package portion and a lower surface of the metal base. It is preferable that the frame portion is inserted in the penetration space after the penetration space is formed in the package portion.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: October 1, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Susumu Iwamoto
  • Patent number: 10424646
    Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A vertical field plate is formed in the trench. The vertical field plate is located between the first sidewall and the second sidewall. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to the first sidewall and a second edge of the gate electrode proximate to the vertical field plate. A dielectric material is formed in the trench between the first sidewall and the vertical field plate. An air cavity is formed in the trench between the vertical field plate and the second sidewall with the air cavity having a dielectric constant lower than that of the dielectric material.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: September 24, 2019
    Assignee: NXP USA, INC.
    Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
  • Patent number: 10424542
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface with a semiconductor element and a second surface opposing the first surface. A first metal layer has a third surface supporting the first semiconductor chip and a fourth surface opposing the third surface. The third surface is larger than the second surface. A resin layer has a fifth surface facing the first semiconductor chip and a sixth surface facing the first metal layer. A pad is on the first surface of the first semiconductor chip. A first via contact is within the resin layer on the third surface of the first metal layer. A second via contact is within the resin layer on the pad. The first and second via contacts are connected to first and the second interconnects, respectively.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: September 24, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kentaro Mori, Chiaki Takubo
  • Patent number: 10418438
    Abstract: A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located between the upper conducting layer and the lower conducting layer, wherein a portion of the dielectric layer (e.g., at least the nitride layer of the ONO layer stack) extends beyond a lateral edge of the upper conducting layer. A method forming such capacitor structure may utilize a spacer adjacent the lateral edge of the upper conducting layer and over the first portion of the dielectric layer, performing an etch to remove a first portion of the dielectric layer but protect a second portion located below the spacer and extending laterally beyond an edge of the upper conducting layer.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 17, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Randy Yach, Rohan Braithwaite
  • Patent number: 10418336
    Abstract: To protect the insulating film so that crack is not produced in the insulating film even when stress is applied to the semiconductor device. A manufacturing method of a semiconductor device is provided, including: forming an insulating film above a semiconductor substrate; forming, in the insulating film, one or more openings that expose the semiconductor substrate; forming a tungsten portion deposited in the openings and above the insulating film; thinning the tungsten portion on condition that the tungsten portion remains in at least part of a region above the insulating film; and forming an upper electrode above the tungsten portion.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Morio Iwamizu
  • Patent number: 10418487
    Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Jessica S. Kachian
  • Patent number: 10418554
    Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tsz W. Chan, D. V. Nirmal Ramaswamy, Qian Tao, Yongjun Jeff Hu, Everett A. McTeer
  • Patent number: 10410953
    Abstract: A power conversion device includes a semiconductor module with switching elements incorporated therein, a plurality of components electrically connected to the semiconductor module, and a laminated cooler provided with a plurality of cooling plates. A laminate is constituted by laminating at least the plurality of cooling plates and the semiconductor module, at least one among the plurality of cooling plates constituting the laminate is a large area cooling plate in which a projected area when viewed from the stacking direction is larger than the other cooling plates, and at least one of the components is a specific arrangement component which, when viewed from the stacking direction, is arranged in a specific position which overlaps the large area cooling plate, and, when viewed from a direction orthogonal to the stacking direction, overlaps with the laminate.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 10, 2019
    Assignee: DENSO CORPORATION
    Inventor: Taijiro Momose
  • Patent number: 10410972
    Abstract: The present disclosure relates to a shielded integrated module, which includes a module substrate with a number of perimeter bond pads, at least one electronic component attached to the module substrate and encapsulated by a mold compound, a number of perimeter vertical shield contacts, and a shielding structure. The perimeter bond pads are surrounding the at least one electronic component and encapsulated by the mold compound. Each perimeter vertical shield contact is coupled to a corresponding perimeter bond pad and extends through the mold compound, such that a top tip of each perimeter vertical shield contact is exposed at a top surface of the mold compound. The shielding structure completely covers the top surface of the mold compound and is in contact with the perimeter vertical shield contacts.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 10, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Mohsen Haji-Rahim, Howard Joseph Holyoak
  • Patent number: 10403545
    Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 10396208
    Abstract: A method of fabricating a top source/drain junction of a vertical transistor includes forming a structure including a bottom source/drain, a fin channel extending vertically from the bottom source/drain, and a gate arranged around the fin channel, the gate including a dielectric layer, a gate metal, and spacers arranged on top and bottom surfaces of the gate; etching to form a recess in a top surface of the fin, the recess having sidewalls that form oblique angles with respect to sidewalls of the fin; forming a top source/drain on the fin and within the recess; doping the top source/drain with a dopant; and annealing to diffuse the dopants from the top source/drain into the fin.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Muthumanickam Sankarapandian, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10396179
    Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xuefeng Liu, Peng Xu, Yongan Xu
  • Patent number: 10395990
    Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Hyun Lee, Jeong Yun Lee, Seung Ju Park, Geum Jung Seong, Young Mook Oh, Seung Soo Hong
  • Patent number: 10388764
    Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A counter-doped portion of a III-V semiconductor material provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where it might otherwise behave as electrically active amphoteric contaminate in the III-V material. In some embodiments, counter-dopants (e.g., acceptor impurities) are introduced in-situ during epitaxial growth of a base portion of a sub-fin structure. With the counter-doped region limited to a base of the sub-fin structure, risk of the counter-dopant atoms thermally diffusing into an active region of a III-V transistor is mitigated.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Matthew V. Metz, Gilbert Dewey, Willy Rachmady, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani