Patents Examined by Mark V. Prenty
  • Patent number: 7298012
    Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A silicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.
    Type: Grant
    Filed: February 11, 2006
    Date of Patent: November 20, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mario M. Pelella, William George En, Eric Paton, Witold P. Maszara
  • Patent number: 7297975
    Abstract: Disclosed is a non-volatile memory cell including a first conductive electrode region, a second conductive electrode region and a memory region disposed therebetween. The memory region includes one or a plurality of metal oxide nanoparticles, which contact and electrically connect the first and the second electrode region via contact locations and which exhibit a bistable resistance properties when applying an external voltage.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: November 20, 2007
    Assignee: Infineon Technologies AG
    Inventor: Klaus Ufert
  • Patent number: 7294889
    Abstract: A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain of first conductivity type are formed in the second well, and second conductivity type MOSFETs including source/drain of second conductivity type in the first well. A third well of second conductivity type is formed at a region under the first wells and the drain of the second conductivity type MOSFETs. The first well is connected to the semiconductor substrate between the first well and the third well.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyuck-Chai Jung
  • Patent number: 7291885
    Abstract: A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at least disposed on the first dielectric layer above the gate. The source/drain is disposed on the channel layer. The source/drain includes a first barrier layer, a conductive layer and a second barrier layer. The first barrier layer is disposed between the conductive layer and the channel layer. The conductive layer is covered with the first barrier layer and the second barrier layer. The source/drain is covered with the second dielectric layer. Accordingly, the variation of electric characters can be reduced. Moreover, a method for fabricating a thin film transistor is also provided.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: November 6, 2007
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Chuan-Yi Wu, Chin-Chuan Lai, Yung-Chia Kuan, Wei-Jen Tai
  • Patent number: 7291898
    Abstract: According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitaxial extension layer extends over the first and second isolation regions. The bipolar transistor further includes a base layer situated on the epitaxial extension layer, where the base layer includes an epitaxial base, and where the epitaxial base includes a usable emitter formation area. The active area has a first width and the usable emitter formation area has a second width, where the second width is at least as large as the first width.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: November 6, 2007
    Assignee: Newport Fab, LLC
    Inventor: Greg D. U'Ren
  • Patent number: 7291872
    Abstract: In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: November 6, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Hikita, Hiroaki Ueno, Yutaka Hirose, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Patent number: 7288798
    Abstract: Disclosed herein is a light module comprising a substrate, at least one light-emitting element on the substrate, a sealing cap on the substrate and covering the light-emitting elements, and a fluid in the space formed among the sealing cap, the light-emitting elements, and the substrate, such that heat dissipation is fast and yellowing of the encapsulating material is retarded.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: October 30, 2007
    Assignee: Lighthouse Technology Co., Ltd
    Inventors: Chih-Chin Chang, Teng-Huei Huang, Chien-Lung Lee
  • Patent number: 7288803
    Abstract: A III-nitride power semiconductor device that includes a current sense electrode.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 30, 2007
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Paul Bridger, Daniel M. Kinzer
  • Patent number: 7288813
    Abstract: A direct-tunneling semiconductor memory device includes a device isolation structure formed on a semiconductor substrate, including a device isolation trench and a device isolation insulation film filling the device isolation trench, a dielectric film covering both sidewall surfaces and a top surface of a floating gate electrode formed on the semiconductor substrate, a conductive part provided on the sidewall surfaces of the floating gate electrode via the dielectric film, the conductor part constituting a part of a control gate electrode, and first and second diffusion regions formed at respective lateral sides of the floating gate electrode, wherein the first and second diffusion regions are formed on a surface of the device isolation groove with offset from a region right underneath the floating gate electrode, the conductive part is formed in the device region with offset from the device isolation trench.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: October 30, 2007
    Assignee: Fujitsu Limited
    Inventors: Kouji Tsunoda, Tatsuya Usuki
  • Patent number: 7285820
    Abstract: A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 23, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Park, Seung-Beom Yoon, Jeong-Uk Han, Seong-Gyun Kim, Sung-Taeg Kang, Bo-Young Seo, Sang-Woo Kang, Sung-Woo Park
  • Patent number: 7285461
    Abstract: Disclosed is a semiconductor device comprises a semiconductor substrate having on its surface a trench, a polycrystalline semiconductor film formed inside the trench, a diffusion layer deposited on a surface region of the semiconductor substrate, and a metal semi-conductor nitride layer interposed between the diffusion layer and the polycrystalline semiconductor film, the metal semiconductor nitride layer including a metal, nitrogen and a semiconductor constituting the semiconductor substrate, and electrically connecting the polycrystalline semiconductor film with the diffusion layer.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: October 23, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasushi Akasaka
  • Patent number: 7285484
    Abstract: A semiconductor device manufacturing method is provided in which, in the dummy gate pattern formation process, the pattern formation process is simplified and costs are reduced. A semiconductor device manufacturing method including: forming a mask element on a substrate; patterning the mask element into a prescribed shape, and forming a depression in the mask element; placing a functional liquid in the depression; drying the functional liquid placed in the depression so as to form a functional film; annealing the functional film; and, removing the mask element so as to form a dummy gate pattern of a residue of the functional liquid.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: October 23, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Suzuki
  • Patent number: 7285470
    Abstract: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 23, 2007
    Assignee: Infineon Technologies AG
    Inventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
  • Patent number: 7282764
    Abstract: A semiconductor device having high ruggedness is provided. The distance Wm2 between buried regions, positioned at the bottoms of different base diffusion regions and face each other, is set smaller than the distance Wm1 between buried regions positioned at the bottom of the same base diffusion region (Wm1>Wm2). An avalanche breakdown occurs under the bottom of the base diffusion region, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region in the base diffusion region, thereby providing high withstand strength against destruction.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: October 16, 2007
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Shinji Kunori, Hiroaki Shishido, Masato Mikawa, Kosuke Ohshima, Masahiro Kuriyama, Mizue Kitada
  • Patent number: 7274043
    Abstract: Light emitting diode systems are disclosed. An optical display system that includes a light emitting diode (LED) and a cooling system is disclosed. The cooling system is configured so that, during use, the cooling system regulates a temperature of the light emitting diode.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: September 25, 2007
    Assignee: Luminus Devices, Inc.
    Inventors: Alexei A. Erchak, Eleftrios Lidorikis, John W. Graff
  • Patent number: 7271427
    Abstract: A liquid crystal display device with a liquid crystal display panel and a backlight, the backlight is formed by stacking a lower electrode, a light emitting layer and an upper layer on one surface of a substrate, one of the lower electrode and the upper electrode have planer pattern, another of the lower electrode and the upper electrode have plurality of large regions and plurality of small regions which connect neighboring two of the plurality of large regions, and width of the small regions is narrower than that of the large regions.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: September 18, 2007
    Assignee: Hitachi Displays, Ltd.
    Inventors: Masaki Tsubokura, Kazuhiko Yanagawa
  • Patent number: 7271430
    Abstract: An image sensor includes a semiconductor substrate of a first conductivity type, a photodiode of a second conductivity type located in the substrate, a hole accumulated device (HAD) region of the first conductivity type located over the photodiode, a thin surface diffusion region formed on the surface of the HAD region, and a transfer gate located over the surface of the substrate adjacent the HAD region. The image sensor further includes a first channel region of the first conductivity type located in the substrate and aligned below the transfer gate, a second channel region of the second conductivity type located in the substrate between said transfer gate and the first channel region, and an floating diffusion region which is located in the substrate and which electrically contacts the second channel region.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: September 18, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan Park, Jong-cheol Shin
  • Patent number: 7271441
    Abstract: The semiconductor device includes a first semiconductor region of a first conductivity type partially extending to a top face of a semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on the second semiconductor region; a fourth semiconductor region of the second conductivity type formed on the second semiconductor region and adjacent to the third semiconductor region; a trench penetrating through the second semiconductor region and the third semiconductor region; a gate insulating film formed on an inner wall of the trench; and a gate electrode formed on the gate insulating film within the trench.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: September 18, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoe Miyata, Shuji Mizokuchi
  • Patent number: 7268405
    Abstract: Disclosed is a flat panel display which comprises a substrate; a gate line formed on the substrate along a predetermined direction; and a gate electrode electrically connected to the gate line, and having a sheet resistance different from the gate line. With this configuration, a wiring resistance of the gate line can be lowered with minimizing the change of the process and without increasing the thickness of the gate line.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: September 11, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Sang-Il Park, Jae-Bon Koo
  • Patent number: 7268428
    Abstract: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of the die extends between the lid and the substrate, contains the thermal compound, and flexes in response to expansion and contraction of both the substrate and the lid during cycling of the semiconductor module. More particularly, either the barrier is formed of a flexible material or has a flexible connection to the substrate and/or to the lid. The barrier effectively contains the thermal compound between the die and the lid and, thereby, provides acceptable and controlled coverage of the thermal compound over the die for heat removal.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: David L. Edwards, Sushumna Iruvanti, Hilton T. Toy, Wei Zou