Abstract: Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.

Abstract: A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.

Abstract: Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.

Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

Abstract: Source/drain contact spacers for improving integrated circuit device performance and methods of forming such are disclosed herein. An exemplary method includes etching an interlayer dielectric (ILD) layer to form a source/drain contact opening that exposes a contact etch stop layer (CESL) disposed over a source/drain feature, depositing a source/drain contact spacer layer that partially fills the source/drain contact opening and covers the ILD layer and the exposed CESL, and etching the source/drain contact spacer layer and the CESL to extend the source/drain contact opening to expose the source/drain feature. The etching forms source/drain contact spacers. The method further includes forming a source/drain contact to the exposed source/drain feature in the extended source/drain contact opening. The source/drain contact is formed over the source/drain contact spacers and fills the extended source/drain contact opening.

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.

Abstract: A HEMT comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; and a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the channel layer comprises: at least a first GaN layer; and a first graded AlGaN layer on the first GaN layer, the Al proportion of the first graded AlGaN layer increasing with the distance from the first GaN layer.

Abstract: A semiconductor device is provided including a plurality of first conductive patterns disposed on a substrate. A first insulating pattern is disposed between the plurality of first conductive patterns. A plurality of second conductive patterns is disposed on the plurality of first conductive patterns. A first memory cell structure is disposed between the plurality of first conductive patterns and the plurality of second conductive patterns. A second insulating pattern is disposed on the first insulating pattern and on a side surface of the first memory cell structure. A first vertical structure is disposed on the first insulating pattern and passing through the second insulating pattern to an upper surface of the substrate. The first insulating pattern has a plurality of recess portions. The plurality of recess portions include a first recess portion and a second recess portion. The first recess portion and the second recess portion have different depths.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same, and it relates to a field of semiconductor technology. The semiconductor device includes a substrate, a semiconductor layer, a dielectric layer, a source, a drain, and a gate, wherein a first face of the gate close to a side of the drain and close to the semiconductor layer has a first curved face. A gate trench corresponding to the gate is provided on the dielectric layer, a material of the gate being filled in the gate trench, and at least a part of a second face of the gate trench in contact with the gate is a second curved face which extends from a surface of the dielectric layer away from the semiconductor layer toward the semiconductor layer.

Abstract: An example apparatus includes forming a working surface of a substrate material. The example apparatus includes trench formed between two semiconductor structures on the working surface of the substrate material. The example apparatus further includes access lines formed on neighboring sidewalls of the semiconductor structures opposing a channel region separating a first source/drain region and a second source/drain region. The example apparatus further includes a time-control formed inhibitor material formed over a portion of the sidewalls of the semiconductor structures. The example apparatus further includes a dielectric material formed over the semiconductor structures to enclose a non-solid space between the access lines.

Abstract: A method for preparation of perovskite quantum dot (PQD)/polymer/ceramic ternary complex includes encapsulation of bifunctional coating including ceramic and polymer. Encapsulation sequence of polymer and ceramic may be altered according to the application. In one scenario, the perovskite quantum dots may be protected with ceramic coating first and further coated with polymer to obtain the perovskite/ceramic/polymer ternary complex. In another scenario, the perovskite quantum dots may be protected with polymer coating first and followed by ceramic coating to obtain the perovskite/polymer/ceramic ternary complex. The PQD ternary complex may provide synergistic effect on improvement of stability towards heat and moisture when compared to existing technology.

Abstract: Provided are a substrate processing method and a device manufactured by using the same, which may improve etch selectivity of an insulating layer deposited on a stepped structure. The substrate processing method includes: forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface; weakening at least a portion of the first layer; forming a second layer on the first layer; and performing an isotropic etching process on the first layer and the second layer.

Abstract: Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500° C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.

Abstract: A laterally switching cell structure including a metal-insulator-metal stack includes an active metal oxide layer including one or more sub-stoichiometric regions. The metal oxide layer includes one or more metal-oxides deposited conformally using a mixed precursor atomic layer deposition process. A graded oxygen profile in the metal oxide layer(s) of the stack including a mirrored impurity density may be formed wherein the sub-stoichiometric region(s) include a relatively high density of impurities obtained as reaction by-products. Arrays of cell structures can be formed with no requirement for a thick active electrode, allowing for more space for a metal fill and optional selector, thereby reducing access resistance.

Abstract: A vertical resistive switching memory device is provided that includes a resistive random access memory (ReRAM) stack embedded in a material stack of alternating layers of an interlayer dielectric material and a recessed electrode material. A selector device encapsulates a portion of the ReRAM stack and is present in an undercut region that is laterally adjacent to each of the recessed electrode material layers of the material stack.

Abstract: An OxRAM oxide based resistive random access memory cell includes a first electrode; a layer M1Oss of a sub-stoichiometric oxide of a first metal; a layer M2N of a nitride of a second metal M2; a layer M3M4O of a ternary alloy of a third metal M3, a fourth metal M4 and oxygen O, or M3M4NO of a quaternary alloy of the third metal M3, the fourth metal M4, nitrogen N and oxygen O and a second electrode. The standard free enthalpy of formation of the ternary alloy M3M4O, noted ?Gf,T0 (M3M4O), or of the quaternary alloy M3M4NO, noted ?Gf,T0 (M3M4NO), is strictly less than the standard free enthalpy of formation of the sub-stoichiometric oxide M1Oss of the first metal M1, noted ?Gf,T0 (M1Oss), itself less than or equal to the standard free enthalpy of formation of any ternary oxynitride M2NO of the second metal M2, noted ?Gf,T0 (M2NO): ?Gf,T0(M3M4O)<?Gf,T0(M1Oss)??Gf,T0(M2NO) or ?Gf,T0(M3M4NO)<?Gf,T0(M1Oss)??Gf,T0(M2NO).

Abstract: An OLED display panel is provided which can control the problem of shedding even in high definition panels. Metal wiring 5 which conducts with an earth line of a flexible printed substrate 15 is provided on a substrate 1. A display area 2 comprised from a plurality of OLED elements is provided at the center of the substrate 1 and four low resistance metal films 3 are provided along each of four edges of the display area 2 on a surface of insulation films 8, 10 at the periphery of the display area 2. Among these, one low resistance metal film 3 conducts with the metal wiring 5 via a 3a.

Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 ?m is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.

Abstract: A semiconductor device includes a plurality of first conductive lines disposed on a substrate, a plurality of second conductive lines intersecting the plurality of first conductive lines, and a plurality of cell structures interposed between the plurality of first conductive lines and the plurality of second conductive lines. At least one among the plurality of cell structures includes a first electrode, a switching element disposed on the first electrode, a second electrode disposed on the switching element, a first metal pattern disposed on the second electrode, a variable resistance pattern interposed between the first metal pattern and at least one among the plurality of second conductive lines, and a first spacer disposed on a sidewall of the variable resistance pattern, a sidewall of the first metal pattern and a sidewall of the second electrode.