Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.

Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of first cells arranged in a first line, and a plurality of second cells arranged in a second line. P-type fin field-effect transistors (FinFETs) of the plurality of first cells share a continuous fin. P-type FinFETs of two adjacent second cells share a discontinuous fin. The continuous fin and the discontinuous fin include different materials. The first line is parallel to the second line.

Abstract: A semiconductor device including a lower layer, a plurality of first interconnection lines extending in a first direction on the lower layer, a plurality of second interconnection lines extending in a second direction intersecting the first direction between the first interconnection lines and connecting the first interconnection lines, the second direction intersecting the first direction, first insulating patterns between the second interconnection lines, and second insulating patterns disposed in the first interconnection lines may be provided. The first interconnection lines include connection regions, to each of which at least one of the second interconnection lines is connected. The second insulating patterns extend into the connection regions.

Abstract: Semiconductor devices and semiconductor cell arrays are provided herein. In some examples, a semiconductor device includes a multi-fin active region, a mono-fin active region, and an isolation feature between the multi-fin active region and the mono-fin active region. The multi-fin active region includes a first plurality of fins, a second plurality of fins parallel to the first plurality of fins, a first n-type field effect transistor (FET), and a first p-type FET. The mono-fin active region abuts the multi-fin active region. The mono-fin active region includes a first fin, a second fin different from the first fin, a second n-type FET, and a second p-type FET. The isolation feature is parallel to the first and second gate structures.

Abstract: An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. Attention is paid to Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by making an emission wavelength of a molecule which donates energy overlap with the longest-wavelength-side local maximum peak of a graph obtained by multiplying an absorption spectrum of a molecule which receives energy by a wavelength raised to the fourth power.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformity formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar.

Abstract: A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.

Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element has a first electrode, a second electrode, a third electrode, and a switching layer. The first electrode is coupled to the switching layer, the second electrode is coupled to a side surface of the switching layer, and the third electrode is coupled to the switching layer.

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.

Abstract: A resistive random access memory structure and its manufacturing method are provided. The resistive random access memory structure includes a substrate having an array region and a peripheral region. A first low-k dielectric layer located in the peripheral region has a dielectric constant of less than 3. Memory cells are located on the substrate and in the array region. A dielectric layer covers the memory cells and fills the space between adjacent memory cells in the array region, and its material layer is different from that of the first low-k dielectric layer. First conductive plugs are located in the dielectric layer and each of them is in contact with one of the memory cells. A dummy memory cell is located at the boundary between the array region and the peripheral region, and the dummy memory cell is not in contact with any one of the first conductive plugs.

Abstract: Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively.

Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.

Abstract: Semiconductor devices include a channel fin having a top surface. A top semiconductor structure, in contact with the entire top surface of the channel fin and having a top portion and a bottom portion, with the top portion of the top semiconductor structure being narrower than the bottom portion. A restraint structure being formed over the bottom portion of the semiconductor structure.

Abstract: A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

Abstract: The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.

Abstract: The present disclosure provides a 1T1R resistive random access memory and a manufacturing method thereof, and a device. The 1T1R resistive random access memory includes: a memory cell array composed of multiple 1T1R resistive random access memory cells, each 1T1R resistive random access memory cell including a transistor and a resistance switching device (30). The transistor includes a channel layer (201), a gate layer (204) insulated from the channel layer (201), and a drain layer (203) and a source layer (202) disposed on the channel layer (201), and the drain layer (203) and the source layer (202) are vertically distributed on the channel layer (201). The resistance change device (30) is disposed near the drain layer (203). The disclosure reduces the area of a transistor, thereby significantly improving the memory density of the resistive random access memory.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

Abstract: A memory device including a first array of rail structures that extend along a first horizontal direction, in which each of the rail structures are formed to serve as a bottom electrode, and a second array of rail structures that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction. Each of the rail structures in the second array are formed to server as a top electrode. The memory device also includes a continuous dielectric memory layer located between the first array of rail structures and the second array of rail structures. The continuous dielectric memory layer providing protection from current leakage between the rail structures of the first array and the rail structures of the second array.